EEWORLDEEWORLDEEWORLD

Part Number

Search

3HPW14-D-0.750

Description
LVPECL Output Clock Oscillator, 0.75MHz Nom, ROHS COMPLIANT, DIP-14/4
CategoryPassive components    oscillator   
File Size89KB,1 Pages
ManufacturerEuroquartz
Websitehttp://www.euroquartz.co.uk/
Environmental Compliance
Download Datasheet Parametric View All

3HPW14-D-0.750 Overview

LVPECL Output Clock Oscillator, 0.75MHz Nom, ROHS COMPLIANT, DIP-14/4

3HPW14-D-0.750 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codecompliant
Other featuresENABLE/DISABLE FUNCTION; COMPLIMENTARY OUTPUT
maximum descent time1.5 ns
Frequency Adjustment - MechanicalNO
frequency stability25%
Installation featuresTHROUGH HOLE MOUNT
Nominal operating frequency0.75 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
Output load50 OHM
physical size20.2mm x 12.8mm x 5.08mm
longest rise time1.5 ns
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountNO
maximum symmetry55/45 %
Base Number Matches1
EURO
QUARTZ
14 pin Dual-in-Line
DESCRIPTION
HPW14 series LVPECL output oscillators cover the frequency range
750kHz to 800MHz. The part contains a high 'Q' fundamental crystal
and multiplier circuit. Integrated Phase jitter 2.6ps typical.
HPW14 PECL OSCILLATORS
750kHz to 800.0MHz
OUTLINE & DIMENSIONS
SPECIFICATION
Frequency Range:
Output Logic
Phase Noise:
Frequency Stability:
Operating Temp Range
Commercial:
Industrial:
Input Voltage:
Output Voltage
High '1':
Low '0':
750.0MHz to 800.0MHz
LVPECL
See table
See table
-10° to +70°C
-40° to +85°C
+3.3VDC ±5%
Vdd -1.025V min.
Vdd -1.620V max.
(RL = 50W to Vdd -2.0V)
Rise/Fall Times:
1.5ns typical
(20% Vdd to 80% Vdd)
Current Consumption (15pF load):
<24MHz:
25mA max.
24.01 to 96MHz:
65mA max.
96.01 to 700MHz:
100mA max.
Load:
50W into Vdd-2.0V
Start-up Time:
5ms typ., 10ms max.
Duty Cycle:
50%±5% (at Vdd -1.3V)
Input Static Discharge Prot:
2kV min.
Storage Temperature Range:
-55°C to +150°C
Ageing:
±3ppm per year max., ±2ppm
thereafter. At T amb +25°C
Enable/Disable
No connection:
Both outputs enabled
Disable:
Both outputs are disabled when
control pad is taken below 0.3V
referenced to ground. Oscillator is
always 'on'. (Special request -
oscillator is off when disabled.)
Enable:
Both Outputs are enabled when
control pad is taken above 0.7 Vcc
referenced to ground.
ABSOLUTE MAXIMUM RATINGS
(Permanent
damage may be caused if operated beyond these limits.)
Supply Voltage Vdd:
+4.6V max.
Input Voltage Vi:
Vss -0.5 min., VDD +0.5V max.
Input Voltage Vo:
Vss -0.5 min., Vdd +0.5V max.
PHASE NOISE (155.250MHz)
Offset
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
dBc/Hz
-65
-95
-120
-125
-121
-120
-140
STABILITY OVER TEMPERATURE RANGE
Stability
±ppm
25
50
100
25
50
100
Temperature Range Order Code
°C
-10 to +70
-10 to +70
-10 to +70
-40 to +85
-40 to +85
-40 to +85
A
B
C
D
E
F
PART NUMBERS
HPW14 oscillator part numbers are derived as follows:
Example:
Supply Voltage
3 = 3.3VDC
Series Designation
Package Style
Stability Code
(See table)
Frequency
3HPW14-A-250.000
JITTER
Integrated Phase Jitter:
2.6ps typical at 155.520MHz
(12kHz to 20MHz)
Period Jitter (RMS):
4.3ps typical at 155.520MHz
Period Jitter (peak to peak): 27ps typical at 155.520MHz
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
MB90092 sub-screen display issue
I now want to use Fujitsu's video overlay MB90092 chip sub-screen display function, and the main screen can display normally. The characters displayed on the sub-screen are garbled. The code is as fol...
245016767 Embedded System
How to draw a pin photodiode pigtail package?
This is the basic information of the photodiode pigtail I use. Now I want to use AD to draw the circuit diagram, but I still don’t know how to draw it? Please give me some advice...
黏三皮黏三皮 PCB Design
Design and implementation of various frequency division methods based on FPGA
Abstract: This paper introduces the process of designing digital circuits using the VHDL hardware description language input method by designing and implementing a general frequency divider that can r...
maker FPGA/CPLD
ez430-f2013 cannot be recognized
After installing the driver for the first time, the emulator can work, but when it is unplugged and then plugged in, it will prompt that Windows cannot recognize it. What is going on?...
月光 Microcontroller MCU
【GD32E231_DIY】-06 SYN7318 speech recognition module information
[i=s]This post was last edited by sf116 on 2019-5-21 20:09[/i] The SYN7318 module integrates speech recognition, speech synthesis and voice wake-up functions. In terms of speech recognition, it suppor...
sf116 GD32 MCU
3 Ways to Speed Up Your Design Cycle Using Brushless DC Motors
The global effort to reduce power consumption is gaining momentum. Many countries require home appliances (see Figure 1) to meet efficiency standards set by organizations such as the China National In...
qwqwqw2088 Analogue and Mixed Signal

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2847  2485  978  981  837  58  51  20  17  31 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号