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IDT54FCT807CT

Description
FCT SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
Categorysemiconductor    logic   
File Size132KB,7 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT54FCT807CT Overview

FCT SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20

IDT54FCT807CT Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage5.25 V
Minimum supply/operating voltage4.75 V
Rated supply voltage5 V
Processing package descriptionSOIC-20
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingtin lead
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
seriesFCT
Enter conditionsSCHMITT trigger
Logic IC typeLow Skew Clock Driver
Number of inverted outputs0.0
Real output number10
propagation delay TPD3.8 ns
Maximum same-side bending0.5000 ns
Max-Min frequency100 MHz
FAST CMOS
1-TO-10
CLOCK DRIVER
Integrated Device Technology, Inc.
IDT54/74FCT807BT/CT
FEATURES:
0.5 MICRON CMOS Technology
Guaranteed low skew < 250ps (max.)
Very low duty cycle distortion < 350ps (max.)
High speed: propagation delay < 2.5ns (max.)
100MHz operation
TTL compatible inputs and outputs
TTL level output voltage swings
1:10 fanout
Output rise and fall time < 1.5ns (max.)
Low input capacitance: 4.5pF typical
High Drive: -32mA I
OH
, 48mA I
OL
ESD > 2000V per MIL STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, Cerpack and
LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT807BT/CT clock driver is built using
advanced dual metal CMOS technology. This low skew clock
driver features 1:10 fanout, providing minimal loading on the
preceding drivers. The IDT54/74FCT807BT/CT offers low
capacitance inputs with hysteresis for improved noise margins.
TTL level outputs and multiple power and grounds reduce
noise. The device also features -32/48mA drive capability for
driving low impedance traces.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
IN
1
2
3
4
5
6
7
8
9
10
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
20
19
18
17
16
15
14
13
12
11
V
CC
O
10
O
9
GND
O
8
V
CC
O
7
GND
O
6
O
5
3017 drw 02
O
1
O
2
GND
O
1
VCC
O
3
O
4
O
2
GND
O
3
O
5
IN
O
6
VCC
O
4
GND
O
7
O
8
O
9
O
10
V
CC
3017 drw 01
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
GND
V
CC
O
1
INDEX
3
4
5
6
7
8
O
2
GND
O
3
V
CC
2
1
20 19
18
17
O
9
GND
O
8
V
CC
O
7
L20-2
O
10
16
15
14
9 10 11 12 13
O
4
O
5
IN
GND
O
6
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC
TOP VIEW
GND
3017 drw 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
OCTOBER 1995
DSC-4242/3
9.3
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