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3DSD3G24VS6262SC

Description
Synchronous DRAM, 128MX24, CMOS, PDSO68, 0.80 MM PITCH, SOP-68
Categorystorage    storage   
File Size145KB,2 Pages
Manufacturer3D PLUS
Download Datasheet Parametric View All

3DSD3G24VS6262SC Overview

Synchronous DRAM, 128MX24, CMOS, PDSO68, 0.80 MM PITCH, SOP-68

3DSD3G24VS6262SC Parametric

Parameter NameAttribute value
Maker3D PLUS
package instructionSSOP,
Reach Compliance Codeunknown
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PDSO-G68
length29.6 mm
memory density3221225472 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width24
Number of functions1
Number of ports1
Number of terminals68
word count134217728 words
character code128000000
Operating modeSYNCHRONOUS
organize128MX24
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Maximum seat height12.3 mm
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
width10.95 mm
Base Number Matches1
MEMORY MODULE
SDRAM 128Mx24-SOP
3D SD3G24VS6262
Synchronous Dynamic Ram
MODULE
3Gbit SDRAM organized as 128Mx24, based on 128Mx4
Pin Assignment (Top View)
SOP 68 (Pitch : 0.80 mm)
Features
- Organized as 128Mx24-bit based on 128Mx4-bit
- Single +3.3 power supply
- Clock frequency: 133MHz (Max)
- LVTTL interface
- Single pulsed /RAS
- Burst Read/Write operation and burst read/single write
operation capability.
- Programmable burst lengths (BL): 1, 2, 4, 8 or full page.
- 2 Variations of burst sequence
-
Sequential ( BL = 1, 2, 4, 8, full page)
-
Interleave ( BL =1, 2, 4, 8 )
- 2 Variations of refresh
-
Auto refresh
-
Self refresh
- Available Temperature Range:
0°C to 70°C
-40°C to+85°C
-
Available with screening option for high reliability
application (Space, etc…)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NC
DQ20
DQ16
DQ12
V
DD
DQ4
V
DDQ
DQ8
DQ0
V
SSQ
DQ5
DQ9
V
DDQ
DQ13
DQ1
V
SSQ
DQ17
V
DD
DQ21
#WE0
#CAS
#RAS
#CS
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
BA0
BA1
A10
A0
A1
A2
A3
V
DD
CKE4
CKE5
#WE1
CKE3
CKE2
CKE1
V
SS
A4
A5
A6
A7
A8
A9
A11
A12
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
CKE0
CLK
DQM
DQ22
V
SS
DQ18
V
DDQ
DQ2
DQ14
V
SSQ
DQ10
DQ6
V
DDQ
DQ3
DQ11
V
SSQ
DQ7
V
SS
DQ15
DQ19
DQ23
#WE2
FUNCTIONAL BLOCK DIAGRAM
General Description
The 3D SD3G24VS6262 is a high-speed highly integrated
Synchronous Dynamic Random Access Memory containing
3,298,534,823,328 bits.
It is organized as a 24-bit bank, each basic die has 6
separate clock enable signals CKE0 ~ CKE5 and 3
separate #WE0 ~#WE2.
The device is manufactured using 3D-PLUS well known
MCM-V patented technology designed for high speed circuit
applications. It is particularity well suited for use in high
reliability, high performance and high density system
applications, such as solid state mass recorder, server or
workstation.
The 3D SD3G24VS6262 is packaged in a 68 pin SOP.
(All other signals are common to the five devices)
SDRAM Memory Module
PRELIMINARY / MMSD24510406S-C
3D Plus SA reserves the right to cancel product or specifications without notice
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