54AC373
•
54ACT373 Octal Transparent Latch with TRI-STATE Outputs
August 1998
54AC373
•
54ACT373
Octal Transparent Latch with TRI-STATE
®
Outputs
General Description
The ’AC/’ACT373 consists of eight latches with TRI-STATE
outputs for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH, the bus output is in the high
impedance state.
Features
n
n
n
n
n
n
I
CC
and I
OZ
reduced by 50%
Eight latches in a single package
TRI-STATE outputs for bus interfacing
Outputs source/sink 24 mA
’ACT373 has TTL-compatible inputs
Standard Microcircuit Drawing (SMD)
— ’AC373: 5962-87555
— ’ACT373: 5962-87556
Logic Symbols
IEEE/IEC
DS100329-1
DS100329-2
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100329
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Connection Diagrams
Pin Assignment for DIP
and Flatpak
Pin Assignment for LCC
DS100329-4
DS100329-3
Functional Description
The ’AC/’ACT373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs
LE
X
H
H
L
OE
H
L
L
L
D
n
X
L
H
X
Outputs
O
n
Z
L
H
O
0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH to Low transition of Latch Enable
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2
Logic Diagram
DS100329-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+ 0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
CDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’AC
’ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
54AC/ACT
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−55˚C to +125˚C
125 mV/ns
±
50 mA
±
50 mA
−65˚C to +150˚C
175˚C
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
®
circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
Symbol
Parameter
V
CC
(V)
V
IH
Minimum High
Level Input
Voltage
V
IL
Maximum Low
Level Input
Voltage
V
OH
Minimum High
Level Output
Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
54AC
T
A
=
−55˚C to +125˚C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
(Note 2)
V
IN
= V
IL
or V
IH
3.0
4.5
5.5
V
OL
Maximum Low
Level Output
Voltage
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
(Note 2)
V
IN
= V
IL
or V
IH
3.0
4.5
5.5
I
IN
Maximum Input
Leakage Current
5.5
0.50
0.50
0.50
V
µA
I
OL
V
I
= V
CC
, GND
12 mA
24 mA
24 mA
V
I
OUT
= 50 µA
V
I
OH
−12 mA
−24 mA
−24 mA
V
I
OUT
= −50 µA
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
Units
Conditions
±
1.0
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4
DC Characteristics for ’AC Family Devices
Symbol
Parameter
V
CC
(V)
I
OZ
Maximum
TRI-STATE
Current
I
OLD
I
OHD
I
CC
(Note 3) Minimum
Dynamic Output
Current
Maximum Quiescent
Supply Current
Note 2:
All outputs loaded, thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
(Continued)
54AC
T
A
=
−55˚C to +125˚C
Guaranteed Limits
Units
Conditions
5.5
5.5
5.5
5.5
±
5.0
50
−50
80.0
µA
mA
mA
µA
V
I
(OE) = V
IL
, V
IH
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND
Note 4:
I
IN
and I
CC
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V V
CC
.
I
CC
for 54AC
@
25˚C is identical to 74AC
@
25˚C.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
54ACT
T
A
=
−55˚C to +125˚C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
(Note 5)
V
IN
= V
IL
or V
IH
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
3.70
4.70
0.1
0.1
(Note 5)
V
IN
= V
IL
or V
IH
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input Leakage
Current
Maximum TRI-STATE
Current
Maximum I
CC
/Input
(Note 6) Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Note 5:
All outputs loaded; thresholds on input associated with output under test.
Note 6:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 7:
I
CC
for 54ACT
@
25˚C is identical to 74ACT
@
25˚C.
Units
Conditions
V
V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
OUT
= 0.1V
or V
CC
− 0.1V
I
OUT
= −50 µA
V
V
I
OH
I
OUT
= 50 µA
−24 mA
−24 mA
0.50
0.50
V
µA
µA
mA
mA
mA
µA
I
OL
V
I
= V
CC
, GND
V
I
= V
IL
, V
IH
V
O
= V
CC
, GND
V
I
= V
CC
− 2.1V
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND
24 mA
24 mA
5.5
5.5
5.5
5.5
5.5
5.5
±
1.0
±
5.0
1.6
50
−50
80.0
5
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