®
X96010
Data Sheet
October 25, 2005
FN8214.1
Sensor Conditioner with Dual Look Up
Table Memory and DACs
FEATURES
• Two Programmable Current Generators
—±3.2 mA max.
—8-bit (256 Step) Resolution
—External Resistor Pins to Set Full Scale Cur-
rent Output
• External Sensor Input (Single Ended)
• Integrated 8-bit A/D Converter
• Internal Voltage Reference with Output/Input
• Temperature Compensation
• EEPROM Look-up Tables
• Hot Pluggable
• Write Protection Circuitry
—Intersil BlockLock™
—Logic Controlled Protection
• 2-wire Bus with 3 Slave Address Bits
• 3V to 5.5V, Single Supply Operation
• Package
—14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
PIN Diode Bias Control
RF PA Bias Control
Temperature Compensated Process Control
Laser Diode Bias Control
Fan Control
Motor Control
Sensor Signal Conditioning
Data Aquisition Applications
Gain vs. Temperature Control
High Power Audio
Open Loop Temperature Compensation
Close Loop Current, Voltage, Pressure, Temper-
ature, Speed, Position Programmable Voltage
sources, electronic loads, output amplifiers, or
function generator
DESCRIPTION
The X96010 is a highly integrated bias controller which
incorporates two digitally controlled Programmable Cur-
rent Generators and temperature compensation with
dedicated look-up tables. All functions of the device are
controlled via a 2-wire digital serial interface.
Two temperature compensated Programmable Cur-
rent Generators, vary the output current with tempera-
ture according to the contents of the associated
nonvolatile look-up table. The look-up table may be
programmed with arbitrary data by the user via the 2-
wire serial port, and an external temperature sensor
may be used to control the output current response.
Ordering Information
PART NUMBER
X96010V14I
X96010V14IZ
(Note)
PART
MARKING
X96010V I
X96010VI Z
TEMP
RANGE (°C)
-40 to 100
-40 to 100
PACKAGE
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
A0
A1
A2
Vcc
WP
SCL
SDA
1
2
3
4
5
6
7
14
13
12
11
10
9
8
I2
VRef
VSense
Vss
R2
R1
I1
TSSOP 14L
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X96010
BLOCK DIAGRAM
Voltage
Reference
VRef
VSense
ADC
Mux
Look-up
Table 1
Control
& Status
SDA
SCL
WP
A2, A1, A0
2-Wire
Interface
Mux
DAC 1
I1
R1
Mux
Look-up
Table 2
Mux
DAC 2
R2
I2
PIN ASSIGNMENTS
TSSOP
Pin
1
2
3
4
5
Pin
Name
A0
A1
A2
Vcc
WP
Pin Description
Device Address Select Pin 0.
This pin determines the LSB of the device address required to com-
municate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor.
Device Address Select Pin 1.
This pin determines the intermediate bit of the device address re-
quired to communicate using the 2-wire interface. The A1 pin has an on-chip pull-down resistor.
Device Address Select Pin 2.
This pin determines the MSB of the device address required to com-
municate using the 2-wire interface. The A2 pin has an on-chip pull-down resistor.
Supply Voltage.
Write Protect Control Pin.
This pin is a CMOS compatible input. When LOW, Write Protection is
enabled preventing any “Write” operation. When HIGH, various areas of the memory can be protect-
ed using the Block Lock bits BL1 and BL0. The WP pin has an on-chip pull-down resistor, which en-
ables the Write Protection when this pin is left floating.
Serial Clock.
This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data
input and output at the SDA pin.
Serial Data.
This pin is the 2-wire interface data into or out of the device. It is TTL compatible when
used as an input, and it is Open Drain when used as an output. This pin requires an external pull up
resistor.
Current Generator 1 Output.
This pin sinks or sources current. The magnitude and direction of the
current is fully programmable and adaptive. The resolution is 8 bits.
Current Programming Resistor 1.
A resistor between this pin and Vss can set the maximum output
current available at pin I1. If no resistor is used, the maximum current must be selected using control
register bits.
Current Programming Resistor 2.
A resistor between this pin and Vss can set the maximum output
current available at pin I2. If no resistor is used, the maximum current must be selected using control
register bits.
Ground.
Sensor Voltage Input.
This voltage input may be used to drive the input of the on-chip A/D converter.
Reference Voltage Input or Output.
This pin can be configured as either an Input or an Output. As
an Input, the voltage at this pin is provided by an external source. As an Output, the voltage at this
pin is a buffered output voltage of the on-chip bandgap reference circuit. In both cases, the voltage
at this pin is the reference for the A/D converter and the two D/A converters.
Current Generator 2 Output.
This pin sinks or sources current. The magnitude and direction of the
current is fully programmable and adaptive. The resolution is 8 bits.
2
FN8214.1
October 25, 2005
6
7
SCL
SDA
8
9
I1
R1
10
R2
11
12
13
Vss
VSense
VRef
14
I2
X96010
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to Vss.
Temperature under bias ................... -65°C to +100°C
Storage temperature ........................ -65°C to +150°C
Voltage on every pin except Vcc
................ -1.0V to +7V
Voltage on Vcc Pin .............................................0 to 5.5V
D.C. Output Current at pin SDA
...................... 0 to 5 mA
D.C. Output Current at pins R1, R2, and
VRef ........................................................ -0.50 to 1 mA
D.C. Output Current at pins I1 and I2 ....... -3.5 to +3.5mA
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Temperature
Temperature while writing to memory
Voltage on Vcc Pin
Voltage on any other Pin
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
Min.
-40
0
3
-0.3
Max.
+100
+70
5.5
Vcc + 0.3
Units
°C
°C
V
V
ELECTRICAL CHARACTERISTICS
(Conditions are as follows, unless otherwise specified)
All typical values are for 25°C ambient temperature and 5V at pin Vcc. Maximum and minimum specifications are over
the recommended operating conditions. All voltages are referred to the voltage at pin Vss. Bit 3 in Control register 0 is
“1”, while all other bits in control registers are “0”. 255Ω, 0.1%, resistor connected between R1 and Vss, and another
between R2 and Vss. 400kHz TTL input at SCL. SDA pulled to Vcc through an external 2kΩ resistor. 2-wire interface
in “standby” (see notes 1 and 2 on page 5). WP, A0, A1, and A2 floating. VRef pin unloaded.
Symbol
Iccstby
Iccfull
Parameter
Standby current into Vcc
pin
Full operation current into
Vcc pin
Min
Typ
Max
2
15
Unit
mA
mA
Test Conditions / Notes
R1 and R2 floating, VRef unloaded.
2-wire interface reading from
memory, I
1
and I
2
both connected to
Vss, DAC input bytes: FFh, VRef
unloaded.
Average from START condition until
t
WP
after the STOP condition
WP: Vcc, R1 and R2 floating,
VRef unloaded.
V(WP), V(A0), V(A1), and V(A2) from
0V to Vcc
Iccwrite
Nonvolatile Write current
into Vcc pin
4
mA
I
PLDN
V
ILTTL
V
IHTTL
I
INTTL
V
OLSDA
I
OHSDA
V
ILCMOS
On-chip pull down current
at WP, A0, A1, and A2
SCL and SDA, input Low
voltage
SCL and SDA, input High
voltage
SCL and SDA input
current
SDA output Low voltage
SDA output High current
WP, A0, A1, and A2 input
Low voltage
0
1
20
0.8
µA
V
V
2.0
-1
0
0
0
10
0.4
100
0.2 x
Vcc
µA
V
µA
V
Pin voltage between 0 and Vcc, and
SDA as an input.
I(SDA) = 2 mA
V(SDA) = Vcc
3
FN8214.1
October 25, 2005
X96010
ELECTRICAL CHARACTERISTICS
(Continued)
(Conditions are as follows, unless otherwise specified)
All typical values are for 25°C ambient temperature and 5V at pin Vcc. Maximum and minimum specifications are over
the recommended operating conditions. All voltages are referred to the voltage at pin Vss. Bit 3 in Control register 0 is
“1”, while all other bits in control registers are “0”. 255Ω, 0.1%, resistor connected between R1 and Vss, and another
between R2 and Vss. 400kHz TTL input at SCL. SDA pulled to Vcc through an external 2kΩ resistor. 2-wire interface
in “standby” (see notes 1 and 2 on page 5). WP, A0, A1, and A2 floating. VRef pin unloaded.
Symbol
V
IHCMOS
VRefout
RVref
TCOref
VRef Range
I
R
V
POR
VccRamp
V
ADCOK
Parameter
WP, A0, A1, and A2 input
High voltage
Output Voltage at VRef at
25°C
VRef pin input resistance
Temperature coefficient of
VRef output voltage
Voltage range when VRef
is an input
Current from pin R1 or R2
to Vss
Power-on reset threshold
voltage
Vcc Ramp Rate
ADC enable minimum
voltage
Min
0.8 x
Vcc
1.205
20
-100
1
0
1.5
0.2
2.6
Typ
Max
Vcc
Unit
V
V
kΩ
ppm/°
C
V
µA
V
mV /
µ
s
V
Test Conditions / Notes
1.21
1.215
40
+100
1.3
3200
2.8
50
2.8
-20
µA ≤
I(VRef)
≤
20
µA
VRM bit = “1”, 25°C
See note 4 and 5.
See note 3.
See Figure 10.
Notes: 1. The device goes into Standby: 200 ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby t
WC
after
a STOP that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the cor-
rect Slave Address Byte.
2. t
WC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
3. For this range of V(VRef) the full scale sink mode current at I1 and I2 follows V(VRef) with a linearity error smaller than 1%.
4. This parameter is periodically sampled and not 100% tested.
5. TCO
ref
= [Max V(V
REF
) - Min V(V
REF
)] x 10
6
/(1.21V x 140°C)
4
FN8214.1
October 25, 2005
X96010
D/A CONVERTER CHARACTERISTICS
(See pg. 4 for Standard Conditions)
Symbol
IFS
Offset
DAC
FSError
DAC
DNL
DAC
INL
DAC
Parameter
I1 or I2 full scale current
I1 or I2 D/A converter offset error
I1 or I2 D/A converter full scale error
I1 or I2 D/A converter
Differential Nonlinearity
I1 or I2 D/A converter Integral Nonlin-
earity with respect to a straight line
through 0 and the full scale value
I1 or I2 Sink Voltage Compliance
I1 or I2 Source Voltage Compliance
I1 or I2 overshoot on D/A Converter
data byte transition
I1 or I2 undershoot on D/A Converter
data byte transition
I1 or I2 rise time on D/A Converter data
byte transition; 10% to 90%
Temperataure coefficient of output
current due to internal parameters
Min
1.56
1
-2
-0.5
-1
Typ
1.58
Max
1.6
3.2
1
2
0.5
1
Unit
mA
mA
LSB
LSB
LSB
LSB
Test Conditions / Notes
See note 1, 5, R = 510Ω
See note 1, 4, 6, R = 255Ω
See notes 2 and 3.
V
ISink
V
ISource
I
OVER
I
UNDER
t
rDAC
TCO
Iout
1.2
2.5
0
0
Vcc
Vcc
Vcc-1.2
Vcc-2.5
0
0
V
V
V
V
µA
µA
µs
ppm/
°C
See note 5
See note 4, 6
See note 5
See note 4, 6
DAC input byte changing from
00h to FFh and vice
versa, V(I1) and V(I2) are
Vcc - 1.2V in source mode
and 1.2V in sink mode.
See note 4.
See Figure 7.
VRMbit = “0”
5
-100
30
+100
Notes: 1. DAC input Byte = FFh, Source or sink mode.
2 V(VRef)
2. LSB is defined as
divided by the resistance between R1 or R2 to Vss.
x
255
3
3. Offset
DAC
: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSError
DAC
: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The Offset
DAC
is subtracted from the measured value before calculating FSError
DAC
.
DNL
DAC
: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNL
DAC
.
INL
DAC
: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
[
]
4. These parameters are periodically sampled and not 100% tested.
5. V(I1) and V(I2) are V
CC
- 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies <1%.
6. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V
CC
= 4.5V. The compliance volt-
age changes to 2.5V from the sourcing rail, and the current variation is <1%.
5
FN8214.1
October 25, 2005
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