Product Specification
PE4239
SPDT UltraCMOS™ RF Switch
Product Description
The PE4239 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from DC through 3.0 GHz. This
reflective switch integrates on-board CMOS control logic with a
low voltage CMOS-compatible control interface, and can be
controlled using either single-pin or complementary control
inputs. Using a nominal +3-volt power supply voltage, a typical
input 1 dB compression point of +27 dBm can be achieved.
The PE4239 UltraCMOS™ RF Switch is manufactured on
Peregrine’s UltraCMOS™ process, a patented variation of
silicon-on-insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
Features
•
Single-pin or complementary CMOS
logic control inputs
•
+3.0-volt power supply needed for
single-pin control mode
•
Low insertion loss: 0.7 dB at 1.0 GHz,
0.9 dB at 2.0 GHz
•
Isolation of 32 dB at 1.0 GHz, 23 dB at
2.0 GHz
•
Typical input 1 dB compression point of
+27 dBm
•
Ultra-small SC-70 package
Figure 2. Package Type SC-70
6-lead SC-70
RF2
RF1
CMOS
Control
Driver
CTRL CTRL or V
DD
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(Z
S
= Z
L
= 50
Ω)
Parameter
Operation Frequency
1
Insertion Loss
Isolation
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Video Feedthrough
2
Input 1 dB Compression
Input IP3
2000 MHz
2000 MHz, 14 dBm input power
26
43
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
50% CTRL to 0.1 dB of final value, 1 GHz
50% CTRL to 25 dB isolation, 1 GHz
30
21
18
16
Conditions
Minimum
DC
Typical
0.7
0.9
32
23
20
18
300
200
15
27
45
Maximum
3000
0.85
1.05
Units
MHz
dB
dB
dB
dB
dB
dB
ns
ns
mV
pp
dBm
dBm
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50
Ω
test
set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Document No. 70-0068-02
│
www.psemi.com
©2002-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 9
PE4239
Product Specification
Figure 3. Pin Configuration (Top View)
pin 1
Table 3. Absolute Maximum Ratings
Symbol
V
DD
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature
range
Operating temperature
range
Input power (50Ω)
ESD voltage (Human
Body Model)
Min
-0.3
-0.3
-65
-40
Max
4.0
V
DD
+
0.3
150
85
30
1500
Units
V
V
°C
°C
dBm
V
RF1
GND
RF2
1
6
CTRL or V
DD
.
239
V
I
5
2
RFC
CTRL
3
4
T
ST
T
OP
P
IN
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
V
ESD
Pin
Name
RF1
GND
RF2
CTRL
RFC
Description
RF1 port (Note 1)
Ground connection. Traces should be
physically short and connected to
ground plane for best performance.
RF2 port (Note 1)
Switch control input, CMOS logic level.
Common RF port for switch (Note 1)
Control Voltage High
This pin supports two interface options:
Single-pin control mode.
A nominal 3-
volt supply connection is required.
Complementary-pin control mode.
A
complementary CMOS control signal
to CTRL is supplied to this pin. By-
passing on this pin is not required in
this mode.
Control Voltage Low
0.7x V
DD
0.3x V
DD
V
V
Table 4. DC Electrical Specifications
Parameter
V
DD
Power Supply
Voltage
I
DD
Power Supply Current
(V
DD
= 3V, V
CTRL
= 3V)
Min
2.7
Typ
3.0
250
Max
3.3
500
Units
V
nA
6
CTRL or
V
DD
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Note 1:
All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
.
©2002-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 9
Document No. 70-0068-02
│
UltraCMOS™ RFIC Solutions
PE4239
Product Specification
Table 5. Single-pin Control Logic Truth Table
Control Voltages
Pin 6 (CTRL or V
DD
) = V
DD
Pin 4 (CTRL) = High
Pin 6 (CTRL or V
DD
) = V
DD
Pin 4 (CTRL) = Low
Signal Path
RFC to RF1
Control Logic Input
The PE4239 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single-pin control mode
enables the switch to
operate with a single control pin (pin 4) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection on pin
6 (V
DD
). This mode of operation reduces the
number of control lines required and simplifies the
switch control interface typically derived from a
CMOS
µProcessor
I/O port.
Complementary-pin control mode
allows the
switch to operate using complementary control
pins CTRL and
CTRL
(pins 4 & 6), that can be
directly driven by +3-volt CMOS logic or a suitable
µProcessor
I/O port. This enables the PE4239 to
be used as a potential alternate source for SPDT
RF switch products used in positive control
voltage mode and operating within the PE4239
operating limits.
RFC to RF2
Table 6. Complementary-pin Control Logic
Truth Table
Control Voltages
Pin 6 (CTRL or V
DD
) = Low
Pin 4 (CTRL) = High
Pin 6 (CTRL or V
DD
) = High
Pin 4 (CTRL) = Low
Signal Path
RFC to RF1
RFC to RF2
Document No. 70-0068-02
│
www.psemi.com
©2002-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 9
PE4239
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4239 SPDT switch. The RF common port is
connected through a 50Ω transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50Ω transmission lines to the
top two SMA connectors on the right side of the
board, J3 and J2, respectively. A through
transmission line connects SMA connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and
ε
r
of 4.4.
J6 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J6-3) is connected
to the device V1 or CTRL input. The fourth pin to
the right (J6-7) is connected to the device V2 or
CTRL/V
DD
input.
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0083
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0104
©2002-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 9
Document No. 70-0068-02
│
UltraCMOS™ RFIC Solutions
PE4239
Product Specification
Typical Performance Data @ -40 °C to 85 °C (Unless otherwise noted)
Figure 6. Insertion Loss – RFC to RF1
Figure 7. Input 1 dB Compression Point & IIP3
(Typical performance @ 25 °C)
0
60
60
-0.3
-40°C
Insertion Loss (dB)
50
50
1dB Compression Point (dBm)
IIP3 (dBm)
-0.6
40
40
-0.9
85°C
25°C
30
30
-1.2
-1.5
0
500
1000
1500
2000
2500
3000
20
0
500
1000
1500
2000
2500
20
3000
Frequency (MHz)
Frequency (MHz)
Figure 8. Insertion Loss – RFC to RF2
Figure 9. Isolation – RFC to RF1
0
0
-0.3
-40°C
Insertion Loss (dB)
-20
-0.9
85°C
25°C
Isolation (dB)
-0.6
-40
-60
-1.2
-80
-1.5
0
500
1000
1500
2000
2500
3000
-100
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
Frequency (MHz)
Document No. 70-0068-02
│
www.psemi.com
©2002-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 9
Power technology
京公网安备 11010802033920号
EEWORLD
