Am79C965A
PCnet™-32 Single-Chip 32-Bit Ethernet Controller
DISTINCTIVE CHARACTERISTICS
s
Single-chip Ethernet controller for 486 and
Video Electronics Standards Association
(VESA) local buses
s
Supports ISO 8802-3 (IEEE/ANSI 802.3) and
Ethernet standards
s
Direct interface to the 486 local bus or VESA
VL-Bus
s
Enhanced burst mode with support for Am486™
burst read/write operations
s
Software-compatible with AMD’s Am7990
LANCE, Am79C90 C-LANCE, Am79C960
PCnet-ISA, Am79C961 PCnet-ISA+, Am79C961A
PCnet-ISA II, Am79C970A PCnet-PCI II, and
Am79C900 ILACC™ register and descriptor
architecture
s
Compatible with Am2100/Am1500T and Novell
NE2100/NE1500 driver software
s
High-performance Bus Master architecture with
integrated DMA buffer management unit for low
CPU and bus utilization
s
Built-in byte-swap logic supports both big and
little endian byte alignment
s
Microwire EEPROM interface supports
jumperless design
s
Single +5 V power supply operation
s
Low-power, CMOS design with sleep modes
allows reduced power consumption for critical
battery-powered applications and Green PCs
s
Look-Ahead Packet Processing (LAPP) allows
protocol analysis to begin before end of receive
frame
s
Integrated Manchester encoder/decoder
s
Individual 136-byte transmit and 128-byte
receive FIFOs provide frame buffering for
increased system latency tolerance and
support the following features:
—Automatic retransmission with no FIFO reload
—Automatic receive stripping and transmit
padding (individually programmable)
—Automatic runt packet rejection
—Automatic deletion of received collision frames
s
JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board-level production test
s
Provides integrated attachment unit interface
(AUI) and 10BASE-T transceiver with automatic
port selection
s
Automatic twisted-pair receive polarity
detection and automatic correction of the
receive polarity
s
Optional byte padding to long-word boundary
on receive
s
Dynamic transmit FCS generation
programmable on a frame-by-frame basis
s
Internal/external loopback capabilities
s
Supports the following types of network
interfaces:
—AUI to external 10BASE-2, 10BASE-5,
10BASE-T or 10BASE-F MAU
—Internal 10BASE-T transceiver with Smart
Squelch to twisted-pair medium
s
Supports LANCE/C-LANCE/PCnet-ISA general
purpose serial interface (GPSI)
s
160-pin PQFP package
GENERAL DESCRIPTION
The PCnet-32 single-chip 32-bit Ethernet controller is a
highly integrated Ethernet system solution designed to
address high-performance system application require-
ments. It is a flexible bus-mastering device that can be
used in any networking application, including network-
ready PCs, printers, fax modems, and bridge/router
designs. The bus-master architecture provides high
data throughput in the system and low CPU and bus
utilization. The PCnet-32 controller is fabricated with
AMD’s advanced low-power CMOS process to provide
low operating and standby current for power-sensitive
applications.
P
ublication#
18219
Rev:
D
Amendment/0
Issue Date:
August 2000
The PCnet-32 controller is a complete Ethernet node
integrated into a single VLSI device. It contains a bus
interface unit, a DMA buffer management unit, an ISO
8802-3 (IEEE/ANSI 802.3)-defined media access con-
trol (MAC) function, individual 136-byte transmit and
128-byte receive FIFOs, an ISO 8802-3 (IEEE/ANSI
802.3)-defined attachment unit interface (AUI) and
twisted-pair transceiver medium attachment unit
(10BASE-T MAU), and a microwire EEPROM interface.
The PCnet-32 controller is also register-compatible
with the LANCE (Am7990) Ethernet controller, the C-
LANCE (Am79C90) Ethernet controller, the ILACC
(Am79C900) Ethernet controller, and all Ethernet
controllers in the PCnet family, including the PCnet-ISA
controller (Am79C960), the PCnet-ISA+ controller
(Am79C961), PCnet-ISA II (Am79C961A), and the
PCnet-PCI II controller (Am79C970A). The buffer man-
a g e m e n t u n i t s u p p o r t s t h e L A N C E , I L AC C
(Am79C900), and PCnet descriptor software models.
The PCnet-32 controller is software-compatible with
Novell NE2100 and NE1500 Ethernet adapter card ar-
chitectures. In addition, a Sleep function has been in-
corporated to provide low standby current, which is
essential for notebooks and Green PCs.
The 32-bit demultiplexed bus interface unit provides a
direct interface to the VESA VL-Bus and 486 series
microprocessors, simplifying the design of an Ethernet
node in a PC system. With its built-in support for both
little and big endian byte alignment, this controller also
addresses proprietary non-PC applications.
Key PCnet-32 configuration parameters, including the
unique IEEE physical address, can be read from an ex-
ternal non-volatile memory (serial EEPROM) immedi-
ately following system reset. In addition, the I/O
location at which the internal registers are accessed
may be stored in the EEPROM, allowing the software
model of the device to be located appropriately in
system I/O space during system initialization.
The controller has the capability to select automatically
either the AUI port or the twisted-pair transceiver. Only
one interface is active at any one time. The individual
transmit and receive FIFOs reduce system overhead,
providing sufficient latency during frame transmission
and reception, and minimizing intervention during
nor mal networ k error recover y. The integrated
Manchester encoder/decoder (MENDEC) eliminates
the need for an external serial interface adapter (SIA)
in the node system. The built-in general purpose serial
interface (GPSI) allows the MENDEC to be bypassed.
In addition, the device provides programmable on-chip
LED drivers for transmit, receive, collision, receive
polarity, link integrity, or jabber status. The PCnet-32
controller also provides an external address detection
interface (EADI) to allow external hardware address
filterin
g in
inter-networking applications.
2
Am79C965A
ORDERING INFORMATION
Standard Products:
AMD standard products are available in several packages and operating ranges. The order number (valid
combination) is formed by a combination of the elements below.
Am79C965A
K
C
\W
ALTERNATIVE PACKAGE OPTION
\W = Trimmed and Formed in a Tray (PQJ160)
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
(per Prod. Nomenclature/16-038)
K = Plastic Quad Flat Pack (PQR160)
SPEED
Not Applicable
DEVICE NUMBER/DESCRIPTION
Am79C965A
PCnet-32 Single-Chip 32-Bit Ethernet Controller
Valid Combinations
Am79C965A
KC, KC\W
Valid Combinations
Valid combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combi-
nations and to check on newly released combinations.
Am79C965A
3
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
BLOCK DIAGRAM: VESA VL-BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CONNECTION DIAGRAM: VESA VL-BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PIN DESIGNATIONS: VESA VL-BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DRIVER TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN DESCRIPTION: VESA VL-BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CONFIGURATION PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CONFIGURATION PIN SETTINGS SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PIN CONNECTIONS TO V
DD
OR V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VESA VL-BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MICROWIRE EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ATTACHMENT UNIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TWISTED PAIR INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
GENERAL PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
POWER SUPPLY PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VESA VL-BUS / LOCAL BUS PIN CROSS-REFERENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
BLOCK DIAGRAM: 486 LOCAL BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CONNECTION DIAGRAM: 486 LOCAL BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PIN DESIGNATIONS: 486 LOCAL BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DRIVER TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PIN DESCRIPTION: 486 LOCAL BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CONFIGURATION PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CONFIGURATION PIN SETTINGS SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PIN CONNECTIONS TO V
DD
OR V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LOCAL BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
BOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MICROWIRE EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ATTACHMENT UNIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TWISTED PAIR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
GENERAL PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
POWER SUPPLY PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SYSTEM BUS INTERFACE FUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SOFTWARE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
BUS ACQUISITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
BUS MASTER DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
INITIALIZATION BLOCK DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DESCRIPTOR DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
FIFO DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
LINEAR BURST DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4
Am79C965A
SLAVE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
VESA VL-BUS MODE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
BUS MASTER AND BUS SLAVE DATA BYTE PLACEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
BUFFER MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
RE-INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
BUFFER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DESCRIPTOR RINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DESCRIPTOR RING ACCESS MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
POLLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TRANSMIT DESCRIPTOR TABLE ENTRY (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
RECEIVE DESCRIPTOR TABLE ENTRY (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
MEDIA ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TRANSMIT AND RECEIVE MESSAGE DATA ENCAPSULATION . . . . . . . . . . . . . . . . . . . . . . . . 91
MEDIA ACCESS MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MANCHESTER ENCODER/DECODER (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EXTERNAL CRYSTAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EXTERNAL CLOCK DRIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
MENDEC TRANSMIT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TRANSMITTER TIMING AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
RECEIVER PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
INPUT SIGNAL CONDITIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CLOCK ACQUISITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PLL TRACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CARRIER TRACKING AND END OF MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DATA DECODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
JITTER TOLERANCE DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ATTACHMENT UNIT INTERFACE(AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DIFFERENTIAL INPUT TERMINATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
COLLISION DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TWISTED-PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TWISTED PAIR TRANSMIT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TWISTED PAIR RECEIVE FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
POLARITY DETECTION AND REVERSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
TWISTED PAIR INTERFACE STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
COLLISION DETECT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SIGNAL QUALITY ERROR (SQE) TEST (HEARTBEAT) FUNCTION . . . . . . . . . . . . . . . . . . . . . . 99
JABBER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10BASE-T INTERFACE CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
BOUNDARY SCAN CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SUPPORTED INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
INSTRUCTION REGISTER AND DECODING LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
OTHER DATA REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EADI (EXTERNAL ADDRESS DETECTION INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
GENERAL PURPOSE SERIAL INTERFACE (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
POWER SAVINGS MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SOFTWARE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I/O REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
HARDWARE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
PCNET-32 CONTROLLER MASTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SLAVE ACCESS TO I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
EEPROM MICROWIRE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Am79C965A
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京公网安备 11010802033920号
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