AT49BV002A datasheet, PDF - EEWORLD Datasheet

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AT49BV002A: Description2-megabit (256K x 8) Single 2.7-volt Battery-Voltage Flash Memory; File Size173KB，19 Pages; ManufacturerAtmel (Microchip)

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AT49BV002A Overview

2-megabit (256K x 8) Single 2.7-volt Battery-Voltage Flash Memory

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Features

•

Single Supply for Read and Write: 2.7 to 3.6V

Fast Read Access Time – 70 ns

Internal Program Control and Timer

Sector Architecture

– One 16K Bytes Boot Block with Programming Lockout

– Two 8K Bytes Parameter Blocks

– Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)

Fast Erase Cycle Time – 4 Seconds

Byte-by-Byte Programming – 30 µs/Byte Typical

Hardware Data Protection

DATA Polling for End of Program Detection

Low Power Dissipation

– 15 mA Active Current

– 50 µA CMOS Standby Current

Typical 10,000 Write Cycles

Green (Pb/Halide-free) Packaging Option

•

2-megabit

(256K x 8)

Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV002A

AT49BV002AN

AT49BV002AT

AT49BV002ANT

1. Description

The AT49BV002A(N)(T) is a 2.7-volt-only in-system reprogrammable Flash Memory.

Its 2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to

70 ns with power dissipation of just 54 mW over the industrial temperature range.

When the device is deselected, the CMOS standby current is less than 50 µA. For the

AT49BV002AN(T) pin 1 for PLCC package and pin 9 for the TSOP package are no

connect pins. To allow for simple in-system reprogrammability, the

AT49BV002A(N)(T) does not require high input voltages for programming. Five-volt-

only commands determine the read and programming operation of the device. Read-

ing data out of the device is similar to reading from an EPROM; it has standard CE,

OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV002A(N)(T)

is performed by erasing a block of data and then programming on a byte by byte

basis. The byte programming time is a fast 30

µs.

The end of a program cycle can be

optionally detected by the DATA polling feature. Once the end of a byte program cycle

has been detected, a new access for a read or program can begin. The typical num-

ber of program and erase cycles is in excess of 10,000 cycles.

The device is erased by executing the erase command sequence; the device inter-

nally controls the erase operations. There are two 8K byte parameter block sections,

four main memory blocks, and one boot block.

The device has the capability to protect the data in the boot block; this feature is

enabled by a command sequence. The 16K-byte boot block section includes a repro-

gramming lock out feature to provide data integrity. The boot sector is designed to

contain user secure code, and when the feature is enabled, the boot sector is pro-

tected from being reprogrammed.

In the AT49BV002AN(T), once the boot block programming lockout feature is

enabled, the contents of the boot block are permanent and cannot be changed. In the

AT49BV002A(T), once the boot block programming lockout feature is enabled, the

contents of the boot block cannot be changed with input voltage levels of 5.5 volts or

less.

3353F–FLASH–3/05

4.3

Reset

A RESET input pin is provided to ease some system applications. When RESET is at a logic

high level, the device is in its standard operating mode. A low level on the RESET input halts the

present device operation and puts the outputs of the device in a high impedance state. If the

RESET pin makes a high to low transition during a program or erase operation, the operation

may not be successfully completed and the operation will have to be repeated after a high level

is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device

returns to the read or standby mode, depending upon the state of the control inputs. By applying

a 12V

0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if

the boot block lockout feature has been enabled (see

“Boot Block Programming Lockout” on

page 5).

The RESET feature is not available on the AT49BV002AN(T).

4.4

Erasure

Before a byte can be reprogrammed, the main memory blocks or parameter blocks which con-

tains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire

device can be erased at one time by using a 6-byte software code. The software chip erase

code consists of 6-byte load commands to specific address locations with a specific data pattern

(please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device will internally time the erase opera-

tion so that no external clocks are required. The maximum time needed to erase the whole chip

is t

. If the boot block lockout feature has been enabled, the data in the boot sector will not be

erased.

4.4.1

Chip Erase

If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block

1, Parameter Block 2, Main Memory Block 1 - 4, but not the boot block. If the Boot Block Lockout

has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase

the device will return back to read mode. Any command during chip erase will be ignored.

4.4.2

Sector Erase

As an alternative to a full chip erase, the device is organized into sectors that can be individually

erased. There are two 8K-byte parameter block sections and four main memory blocks. The 8K-

byte parameter block sections and the four main memory blocks can be independently erased

and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector

address is latched on the rising WE edge of the sixth cycle and the 30H data input command is

also latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the

sixth cycle. The erase operation is internally controlled; it will automatically time to completion.

4.5

Byte Programming

Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte

basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations

can convert “0”s to “1”s. Programming is accomplished via the internal device command register

and is a 4 bus cycle operation (please refer to the

“Command Definition Table” on page 7).

The

device will automatically generate the required internal program pulses.

AT49BV002A(N)(T)

3353F–FLASH–3/05

AT49BV002A(N)(T)

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs

last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming

is completed after the specified t

cycle time. The DATA polling feature may also be used to

indicate the end of a program cycle.

4.6

Boot Block Programming Lockout

The device has one designated block that has a programming lockout feature. This feature pre-

vents programming of data in the designated block once the feature has been enabled. The size

of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that

is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the

device while data in the rest of the device is updated. This feature does not have to be activated;

the boot block’s usage as a write protected region is optional to the user. The address range of

the boot block is 00000 to 03FFF for the AT49BV002A(N) while the address range of the boot

block is 3C000 to 3FFFF for the AT49BV002A(N)T.

Once the feature is enabled, the data in the boot block can no longer be erased or programmed

with input voltage of 5.5V or less. Data in the main memory block can still be changed through

the regular programming method. To activate the lockout feature, a series of six program com-

mands to specific addresses with specific data must be performed. Please refer to the

“Command Definition Table” on page 7.

4.6.1

Boot Block Lockout Detection

A software method is available to determine if programming of the boot block section is locked

out. When the device is in the software product identification mode (see

“Software Product Iden-

tification Entry and Exit”

sections) a read from address location 00002H will show if

programming the boot block is locked out for the AT49BV002A(N), and a read from address

location 3C002H will show if programming the bootblock is locked out for AT49BV002A(N)T. If

the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the pro-

gram lockout feature has been activated and the block cannot be programmed. The software

product identification code should be used to return to standard operation.

Boot Block Programming Lockout Override

The user can override the boot block programming lockout by taking the RESET pin to 12 volts

during the entire chip erase, sector erase or byte programming operation. When the RESET pin

is brought back to TTL levels the boot block programming lockout feature is again active. This

feature is not available on the AT49BV002AN(T).

4.6.2

4.7

Product Identification

The product identification mode identifies the device and manufacturer as Atmel. It may be

accessed by hardware or software operation. The hardware operation mode can be used by an

external programmer to identify the correct programming algorithm for the Atmel product.

For details, see

“Operating Modes” on page 8

(for hardware operation) or Software Product

Identification. The manufacturer and device code is the same for both modes.

3353F–FLASH–3/05

AT49BV002A Related Products

	AT49BV002A	AT49BV002AN	AT49BV002ANT	AT49BV002AT
Description	2-megabit (256K x 8) Single 2.7-volt Battery-Voltage Flash Memory	2-megabit (256K x 8) Single 2.7-volt Battery-Voltage Flash Memory	2-megabit (256K x 8) Single 2.7-volt Battery-Voltage Flash Memory	2-megabit (256K x 8) Single 2.7-volt Battery-Voltage Flash Memory

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