DS1315EN-33/TR datasheet, PDF - EEWORLD Datasheet

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DS1315EN-33/TR: DescriptionTimer or RTC,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size407KB，21 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

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DS1315EN-33/TR Overview

Timer or RTC,

DS1315EN-33/TR Parametric

Parameter Name	Attribute value
Maker	DALLAS
Reach Compliance Code	unknown
Base Number Matches	1

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www.dalsemi.com

www.maxim-ic.com

DS1315

Phantom Time Chip

FEATURES

Real time clock keeps track of hundredths of

seconds, seconds, minutes, hours, days, date

of the month, months, and years

Adjusts for months with fewer than 31 days

Automatic leap year correction valid up to

2100

No address space required to communicate

with RTC

Provides nonvolatile controller functions for

battery backup of SRAM

Supports redundant battery attachment for

high–reliability applications

Full ±10% V

operating range

+3.3 volt or +5 volt operation

Industrial (–45°C to +85°C) operating

temperature ranges available

Drop in replacement for DS1215

DESCRIPTION

The DS1315 Phantom Time Chip is a

combination of a CMOS timekeeper and a

nonvolatile memory controller. In the absence of

power, an external battery maintains the

timekeeping operation and provides power for a

CMOS static RAM. The watch keeps track of

hundredths of seconds, seconds, minutes, hours,

day, date, month, and year information. The last

day of the month is automatically adjusted for

months with less than 31 days, including leap

year correction. The watch operates in one of two

formats: a 12-hour mode with an AM/PM

indicator or a 24-hour mode. The nonvolatile

controller supplies all the necessary support

circuitry to convert a CMOS RAM to a

nonvolatile memory. The DS1315 can be

interfaced with either RAM or ROM without

leaving gaps in memory.

PIN CONFIGURATIONS

BAT1

GND

16-Pin DIP (300-mil)

Pin Configurations continued at end of data sheet.

PIN DESCRIPTION

X1, X2

CC1

CC0

BAT2

RST

CEI

CEO

ROM/RAM

BAT1

GND

ROM/

RAM

CEO

CEI

RST

BAT2

CC0

CC1

- 32.768 kHz Crystal Connection

- Write Enable

- Battery 1 Input

- Ground

- Data Input

- Data Output

- ROM/RAM Mode Select

- Chip Enable Output

- Chip Enable Input

- Output Enable

- Reset

- Battery 2 Input

- Switched Supply Output

- Power Supply Input

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

1 of 21

REV: 040203

DS1315 Phantom Time Chip

Operation

Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits

which must be matched by executing 64 consecutive write cycles containing the proper data on data in

(D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the

chip enable output pin (

CEO

After recognition is established, the next 64 read or write cycles either extract or update data in the Time

Chip and

CEO

remains high during this time, disabling the connected memory.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control

of chip enable input (

CEI

), output enable (

), and write enable (

). Initially, a read cycle using the

CEI

and

control of the Time Chip starts the pattern recognition sequence by moving pointer to the

first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the

CEI

and

control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.

When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match

is found, the pointer increments to the next location of the comparison register and awaits the next write

cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If

a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the

comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as

described above until all the bits in the comparison register have been matched. (This bit pattern is shown

in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the

timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on

D, or transmit data on Q, depending on the level of

pin or the

pin. Cycles to other locations

outside the memory block can be interleaved with

CEI

cycles without interrupting the pattern recognition

sequence or data transfer sequence to the Time Chip.

A standard 32.768 kHz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (X1, X2).

The crystal selected for use should have a specified load capacitance (C

) of 6 pF. For more information

on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal

Considerations with Dallas Real Time Clocks.”

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DS1315EN-33/TR Related Products

	DS1315EN-33/TR	DS1315S-5/TR	DS1315EN-5/TR
Description	Timer or RTC,	Timer or RTC,	Timer or RTC,
Maker	DALLAS	DALLAS	DALLAS
Reach Compliance Code	unknown	unknown	unknown
Base Number Matches	1	1	1

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