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EP312PC-30

Description
OT PLD, 30ns, PAL-Type, CMOS, PDIP24, PLASTIC, DIP-24
CategoryProgrammable logic devices    Programmable logic   
File Size329KB,18 Pages
ManufacturerAltera (Intel)
Download Datasheet Parametric Compare View All

EP312PC-30 Overview

OT PLD, 30ns, PAL-Type, CMOS, PDIP24, PLASTIC, DIP-24

EP312PC-30 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAltera (Intel)
Parts packaging codeDIP
package instructionDIP, DIP24,.3
Contacts24
Reach Compliance Codeunknown
ECCN codeEAR99
Other features12 MACROCELLS
ArchitecturePAL-TYPE
maximum clock frequency50 MHz
JESD-30 codeR-PDIP-T24
JESD-609 codee0
length31.6865 mm
Dedicated input times8
Number of I/O lines12
Number of entries22
Output times12
Number of product terms200
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
organize8 DEDICATED INPUTS, 12 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programmable logic typeOT PLD
propagation delay30 ns
Certification statusNot Qualified
Maximum seat height4.318 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
®
EP312 & EP324
Classic EPLDs
Data Sheet
April 1995, ver. 1
Features
s
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High-performance EPLDs with 12 macrocells (EP312) or 24
macrocells (EP324)
Combinatorial speeds as fast as 25 ns
Counter frequencies of up to 33.3 MHz
Pipelined data rates of up to 66 MHz
Multiple 20-pin PAL and GAL replacement and integration
Device erasure and reprogramming with advanced, nonvolatile
EPROM configuration elements
Programmable registers providing D, T, JK, and SR flipflops with
individual Clear and Clock controls
Dual feedback on all macrocells for implementing buried registers
with bidirectional I/O
Programmable-AND/allocatable-OR structure allowing up to 16
product terms per macrocell
Two product terms on all macrocell control signals
Programmable inputs (8 in EP312, 10 in EP324) configurable as
latches, registers, or flow-through input
Available in windowed ceramic and one-time-programmable (OTP)
plastic packages with 24 to 44 pins:
24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
28-pin plastic J-lead chip carrier (PLCC)
40-pin CerDIP and PDIP
44-pin PLCC
One global Clock pin; one global Input Latch Enable/Input
Clock/Input (ILE/ICLK/INPUT) pin
Programmable “standby” option for low-power operation
Programmable Security Bit for total protection of proprietary designs
100% generically testable to provide 100% programming yield
Software design support with the Altera PLDshell Plus software and
a wide range of third-party tools; programming support through
third-party vendors
General
Description
The CMOS EPROM EP312 and EP324 devices have a versatile macrocell
structure and I/O architecture, which allow them to implement high-
performance logic functions effectively. The EP312 and EP324 input and
macrocell features are a superset of features offered by PAL/GAL
devices. Therefore, EP312 and EP324 devices can be used as an alternative
to multiple PAL/GAL devices, SSI and MSI logic devices, or low-end gate
arrays.
1
Altera Corporation
A-DS-312/324.01

EP312PC-30 Related Products

EP312PC-30 EP312PC-25 EP312DC-30 EP312LI-30 EP312DC-25 EP324PC-25 EP324PC-30
Description OT PLD, 30ns, PAL-Type, CMOS, PDIP24, PLASTIC, DIP-24 OT PLD, 25ns, PAL-Type, CMOS, PDIP24, PLASTIC, DIP-24 UV PLD, 30ns, PAL-Type, CMOS, CDIP24, CERDIP-24 OT PLD, 30ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28 UV PLD, 25ns, PAL-Type, CMOS, CDIP24, CERDIP-24 OT PLD, 25ns, PAL-Type, CMOS, PDIP40, PLASTIC, DIP-40 OT PLD, 30ns, PAL-Type, CMOS, PDIP40, PLASTIC, DIP-40
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Parts packaging code DIP DIP DIP QLCC DIP DIP DIP
package instruction DIP, DIP24,.3 DIP, DIP24,.3 DIP, DIP24,.3 QCCJ, LDCC28,.5SQ DIP, DIP24,.3 DIP, DIP40,.6 DIP, DIP40,.6
Contacts 24 24 24 28 24 40 40
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown
Other features 12 MACROCELLS 12 MACROCELLS 12 MACROCELLS 12 MACROCELLS 12 MACROCELLS 24 MACROCELLS 24 MACROCELLS
Architecture PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE PAL-TYPE
maximum clock frequency 50 MHz 66 MHz 50 MHz 50 MHz 66 MHz 66 MHz 50 MHz
JESD-30 code R-PDIP-T24 R-PDIP-T24 R-GDIP-T24 S-PQCC-J28 R-GDIP-T24 R-PDIP-T40 R-PDIP-T40
JESD-609 code e0 e0 e0 e0 e0 e0 e0
Dedicated input times 8 8 8 8 8 8 8
Number of I/O lines 12 12 12 12 12 24 24
Number of entries 22 22 22 22 22 36 36
Output times 12 12 12 12 12 24 24
Number of product terms 200 200 200 200 200 394 394
Number of terminals 24 24 24 28 24 40 40
Maximum operating temperature 70 °C 70 °C 70 °C 85 °C 70 °C 70 °C 70 °C
organize 8 DEDICATED INPUTS, 12 I/O 8 DEDICATED INPUTS, 12 I/O 8 DEDICATED INPUTS, 12 I/O 8 DEDICATED INPUTS, 12 I/O 8 DEDICATED INPUTS, 12 I/O 8 DEDICATED INPUTS, 24 I/O 8 DEDICATED INPUTS, 24 I/O
Output function MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
Package body material PLASTIC/EPOXY PLASTIC/EPOXY CERAMIC, GLASS-SEALED PLASTIC/EPOXY CERAMIC, GLASS-SEALED PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP DIP DIP QCCJ DIP DIP DIP
Encapsulate equivalent code DIP24,.3 DIP24,.3 DIP24,.3 LDCC28,.5SQ DIP24,.3 DIP40,.6 DIP40,.6
Package shape RECTANGULAR RECTANGULAR RECTANGULAR SQUARE RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE IN-LINE IN-LINE CHIP CARRIER IN-LINE IN-LINE IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED 220 220 220 220 220
power supply 5 V 5 V 5 V 5 V 5 V 5 V 5 V
Programmable logic type OT PLD OT PLD UV PLD OT PLD UV PLD OT PLD OT PLD
propagation delay 30 ns 25 ns 30 ns 30 ns 25 ns 25 ns 30 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum supply voltage 5.25 V 5.25 V 5.25 V 5.5 V 5.25 V 5.25 V 5.25 V
Minimum supply voltage 4.75 V 4.75 V 4.75 V 4.5 V 4.75 V 4.75 V 4.75 V
Nominal supply voltage 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount NO NO NO YES NO NO NO
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE J BEND THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal pitch 2.54 mm 2.54 mm 2.54 mm 1.27 mm 2.54 mm 2.54 mm 2.54 mm
Terminal location DUAL DUAL DUAL QUAD DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 30 30 NOT SPECIFIED NOT SPECIFIED
Base Number Matches 1 1 1 1 1 1 1
Is it lead-free? Contains lead Contains lead - Contains lead Contains lead - -
Maker Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel) - -
ECCN code EAR99 EAR99 - EAR99 EAR99 EAR99 EAR99
length 31.6865 mm 31.6865 mm - 11.5062 mm - 52.4256 mm 52.4256 mm
Maximum seat height 4.318 mm 4.318 mm - 4.572 mm - 4.826 mm 4.826 mm
width 7.62 mm 7.62 mm - 11.5062 mm - 15.24 mm 15.24 mm
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