IDT70125S55J datasheet, PDF - EEWORLD Datasheet

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IDT70125S55J: DescriptionHIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT; File Size133KB，12 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70125S55J Overview

HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

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HIGH-SPEED

2K x 9 DUAL-PORT

STATIC RAM WITH BUSY & INTERRUPT

Integrated Device Technology, Inc.

IDT70121S/L

IDT70125S/L

FEATURES:

• High-speed access

– Commercial: 25/35/45/55ns (max.)

• Low-power operation

– IDT70121/70125S

Active: 500mW (typ.)

Standby: 5mW (typ.)

– IDT70121/70125L

Active: 500mW (typ.)

Standby: 1mW (typ.)

• Fully asychronous operation from either port

• MASTER IDT70121 easily expands data bus width to 18

bits or more using SLAVE IDT70125 chip

• On-chip port arbitration logic (IDT70121 only)

•

BUSY

output flag on Master;

BUSY

input on Slave

•

INT

flag for port-to-port communication

• Battery backup operation—2V data retention

• TTL-compatible, signal 5V (±10%) power supply

• Available in 52-pin PLCC

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port

Static RAMs. The IDT70121 is designed to be used as a

stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port

RAM together with the IDT70125 “SLAVE” Dual-Port in 18-

bit-or-more word width systems. Using the IDT MASTER/

SLAVE Dual-Port RAM approach in 18-bit-or-wider memory

system applications results in full-speed, error-free operation

without the need for additional discrete logic.

Both devices provide two independent ports with separate

control, address, and I/O pins that permit independent, asyn-

chronous access for reads or writes to any location in memory.

An automatic power-down feature, controlled by

, permits

the on-chip circuitry of each port to enter a very low standby

power mode.

The IDT70121/IDT70125 utilizes a 9-bit wide data path to

allow for Data/Control and parity bits at the user’s option. This

feature is especially useful in data communications

applications where it is necessary to use a parity bit for

transmission/reception error checking.

FUNCTIONAL BLOCK DIAGRAM

I/O

- I/O

I/O

Control

I/O

Control

I/O

-I/O

BUSY

(1,2)

BUSY

Address

Decoder

(1,2)

10L

MEMORY

ARRAY

Address

Decoder

11R

NOTES:

1. 70121 (MASTER):

BUSY

is non-tri-

stated push-pull

output.

70125 (SLAVE):

BUSY

is input.

INT

is totem-pole

output.

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

INT

L(2)

INT

2654 drw 01

(2)

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

OCTOBER 1996

DSC-2654/4

6.10

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