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IDT7025L70JB

Description
8K X 16 DUAL-PORT SRAM, 25 ns, CPGA84
Categorystorage   
File Size233KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT7025L70JB Overview

8K X 16 DUAL-PORT SRAM, 25 ns, CPGA84

IDT7025L70JB Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals84
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
maximum access time25 ns
Processing package descriptionCERAMIC, PGA-84
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeGRID ARRAY
Terminal formPIN/PEG
Terminal spacing2.54 mm
terminal coatingTIN LEAD
Terminal locationPERPENDICULAR
Packaging MaterialsCERAMIC, METAL-SEALED COFIRED
Temperature levelMILITARY
memory width16
organize8K X 16
storage density131072 deg
operating modeASYNCHRONOUS
Number of digits8192 words
Number of digits8K
Memory IC typeDUAL-PORT SRAM
serial parallelPARALLEL
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7025S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7025S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7025L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7025 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack
Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/
W
L
R/
W
R
UB
L
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
(1,2)
L
BUSY
R
Address
Decoder
13
(1,2)
A
12L
A
0L
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
NOTES:
1. (MASTER):
BUSY
is output;
(SLAVE):
BUSY
is input.
2.
BUSY
outputs
and
INT
outputs
are non-tri-stated
push-pull.
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R(2)
2683 drw 01
M/
S
The IDT logo is a registered trademark of Integrated Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC 2683/6
6.16
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