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IDT7026S35J

Description
16K X 16 DUAL-PORT SRAM, 25 ns, CPGA84
Categorystorage   
File Size187KB,18 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT7026S35J Overview

16K X 16 DUAL-PORT SRAM, 25 ns, CPGA84

IDT7026S35J Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals84
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
maximum access time25 ns
Processing package descriptionCERAMIC, PGA-84
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeGRID ARRAY
Terminal formPIN/PEG
Terminal spacing2.54 mm
terminal coatingTIN LEAD
Terminal locationPERPENDICULAR
Packaging MaterialsCERAMIC, METAL-SEALED COFIRED
Temperature levelMILITARY
memory width16
organize16K X 16
storage density262144 deg
operating modeASYNCHRONOUS
Number of digits16384 words
Number of digits16K
Memory IC typeDUAL-PORT SRAM
serial parallelPARALLEL
HIGH-SPEED
16K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7026S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 25/35/55ns (max.)
— Commercial: 20/25/35/55ns (max.)
• Low-power operation
— IDT7026S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7026L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7026 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
• M/
S
= H for
BUSY
output flag on Master,
M/
S
= L for
BUSY
input on Slave
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• TTL-compatible, single 5V (±10%) power supply
• Available in 84-pin PGA and 84-pin PLCC
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
14
(1,2)
A
13L
A
0L
MEMORY
ARRAY
14
Address
Decoder
A
13R
A
0R
CE
L
ARBITRATION
SEMAPHORE
LOGIC
CE
R
SEM
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs are non-tri-stated push-pull.
M/
S
SEM
R
2939 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC 2939/3
6.17
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