IDT70T3339S133DD datasheet, PDF

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IDT70T3339S133DD: Description512K X 18 DUAL-PORT SRAM, 15 ns, PBGA256; Categorystorage; File Size320KB，27 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70T3339S133DD Overview

512K X 18 DUAL-PORT SRAM, 15 ns, PBGA256

IDT70T3339S133DD Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	256
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	2.6 V
Minimum supply/operating voltage	2.4 V
Rated supply voltage	2.5 V
maximum access time	15 ns
Processing package description	17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
state	ACTIVE
packaging shape	SQUARE
Package Size	GRID ARRAY, LOW PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	TIN LEAD
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	18
organize	512K X 18
storage density	9.44E6 deg
operating mode	SYNCHRONOUS
Number of digits	524288 words
Number of digits	512K
Memory IC type	DUAL-PORT SRAM
serial parallel	PARALLEL

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HIGH-SPEED 2.5V

IDT70T3339/19/99S

512/256/128K X 18

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– Data input, address, byte enable and control registers

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data,

and address inputs @ 200MHz

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine

pitch Ball Grid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B

0 1

L L

B B

1 0

R R

1/0

R/W

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

FT/PIPE

0/1

0a 1a 0b

0/1

FT/PIPE

512/256/128K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

18L

(1)

REPEAT

ADS

CNTEN

18R

(1)

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

INTERRUPT

COLLISION

DETECTION

LOGIC

0 R

CE1 R

JTAG

TDO

COL

INT

(2)

COL

INT

CONTROL

LOGIC

(2)

5652 drw 01

NOTES:

1. Address A

is a NC for the IDT70T3319. Also, Addresses A

and A

are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

FEBRUARY 2018

DSC-5652/9

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