IDT70T651S8BC datasheet, PDF - EEWORLD Datasheet

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IDT70T651S8BC: Description256K X 36 DUAL-PORT SRAM, 10 ns, PBGA256; Categorystorage; File Size346KB，27 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70T651S8BC Overview

256K X 36 DUAL-PORT SRAM, 10 ns, PBGA256

IDT70T651S8BC Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	256
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	2.6 V
Minimum supply/operating voltage	2.4 V
Rated supply voltage	2.5 V
maximum access time	10 ns
Processing package description	BGA-256
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY, LOW PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	TIN LEAD
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	36
organize	256K X 36
storage density	9.44E6 deg
operating mode	ASYNCHRONOUS
Number of digits	262144 words
Number of digits	256K
Memory IC type	DUAL-PORT SRAM
serial parallel	PARALLEL

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Features

◆

HIGH-SPEED 2.5V

256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

PRELIMINARY

IDT70T651/9S

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T651/9 easily expands data bus width to 72 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

◆

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad

Flatpack and 208-ball fine pitch Ball Grid Array.

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

BBBB

EEEE

3210

R RRR

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_L Dout18-26_R

Dout27-35_L Dout27-35_R

256/128K x 36

MEMORY

ARRAY

I/O

0L-

I/O

35L

Di n_L

Di n_R

I/O

0R -

I/O

35R

17L(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

17R(1)

R/W

BUSY

L (2,3)

SEM

INT

L(3)

(4)

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

TDI

TD O

JTAG

TC K

TMS

TRST

M/S

BUSY

R(2,3)

SEM

INT

R(3)

(4)

NOTES:

1. Address A

17x

is a NC for IDT70T659.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,

INTx,

M/S and the sleep

mode pins themselves (ZZx) are not affected during sleep mode.

CONTROL

LOGIC

4869 drw 01

NOVEMBER 2003

DSC-5632/3

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