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IDT70T659S15BC

Description
256K X 36 DUAL-PORT SRAM, 10 ns, PBGA256
Categorystorage   
File Size346KB,27 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT70T659S15BC Overview

256K X 36 DUAL-PORT SRAM, 10 ns, PBGA256

IDT70T659S15BC Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals256
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage2.6 V
Minimum supply/operating voltage2.4 V
Rated supply voltage2.5 V
maximum access time10 ns
Processing package descriptionBGA-256
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeGRID ARRAY, LOW PROFILE
surface mountYes
Terminal formBALL
Terminal spacing1 mm
terminal coatingTIN LEAD
Terminal locationBOTTOM
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
memory width36
organize256K X 36
storage density9.44E6 deg
operating modeASYNCHRONOUS
Number of digits262144 words
Number of digits256K
Memory IC typeDUAL-PORT SRAM
serial parallelPARALLEL
Features
HIGH-SPEED 2.5V
256/128K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
PRELIMINARY
IDT70T651/9S
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T651/9 easily expands data bus width to 72 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad
Flatpack and 208-ball fine pitch Ball Grid Array.
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
BE
3L
BE
2L
BE
1L
BE
0L
BE
3R
BE
2R
BE
1R
BE
0R
R/
W
L
CE
0L
CE
1L
BB
EE
01
LL
BB
EE
23
LL
BBBB
EEEE
3210
R RRR
R/
W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
OE
R
256/128K x 36
MEMORY
ARRAY
I/O
0L-
I/O
35L
Di n_L
Di n_R
I/O
0R -
I/O
35R
A
17L(1)
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
17R(1)
A
0R
CE
0L
CE
1L
OE
L
R/W
L
BUSY
L (2,3)
SEM
L
INT
L(3)
ZZ
L
(4)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
R/W
R
CE
0R
CE
1R
TDI
TD O
JTAG
TC K
TMS
TRST
M/S
BUSY
R(2,3)
SEM
R
INT
R(3)
ZZ
R
(4)
NOTES:
1. Address A
17x
is a NC for IDT70T659.
2.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
3.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,
INTx,
M/S and the sleep
mode pins themselves (ZZx) are not affected during sleep mode.
ZZ
CONTROL
LOGIC
4869 drw 01
NOVEMBER 2003
DSC-5632/3
1
©2003 Integrated Device Technology, Inc.
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