IDT70V06S15G datasheet, PDF - EEWORLD Datasheet

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IDT70V06S15G: Description16K X 8 DUAL-PORT SRAM, 25 ns, PQFP64; Categorystorage; File Size173KB，22 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT70V06S15G Overview

16K X 8 DUAL-PORT SRAM, 25 ns, PQFP64

IDT70V06S15G Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
maximum access time	25 ns
Processing package description	TQFP-64
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.8000 mm
terminal coating	TIN LEAD
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	8
organize	16K X 8
storage density	131072 deg
operating mode	ASYNCHRONOUS
Number of digits	16384 words
Number of digits	16K
Memory IC type	DUAL-PORT SRAM
serial parallel	PARALLEL

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HIGH-SPEED 3.3V

16K x 8 DUAL-PORT

STATIC RAM

Features

IDT70V06S/L

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25/35/55ns (max.)

Low-power operation

– IDT70V06S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V06L

Active: 380mW (typ.)

Standby: 660mW (typ.)

IDT70V06 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

M/S = V

for

BUSY

output flag on Master

M/S = V

for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation—2V data retention

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PGA and PLCC, and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

I/O

- I/O

I/O

Control

I/O

Control

I/O

-I/O

BUSY

(1,2)

BUSY

Address

Decoder

(1,2)

13L

MEMORY

ARRAY

Address

Decoder

13R

SEM

INT

(2)

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

INT

(2)

2942 drw 01

MARCH 2000

DSC-2942/7

6.07

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