CMOS STATIC RAM
256K (32K x 8-BIT)
Integrated Device Technology, Inc.
IDT71256SA70
FEATURES:
• 32K x 8 CMOS static RAM
• Equal access and cycle times
-- Commercial: 70ns
• One Chip Select plus one Output Enable pin
• Bidirectional data inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Available in 28-pin 30 mil Plastic SOJ, 28-pin 300 mil
Plastic Dip, 28-pin 300 mil TSOP Type I, and 28-pin 600
mil Plastic Dip.
DESCRIPTION:
The IDT71256SA is a 262,144-bit medium-speed Static
RAM organized as 32K x 8. It is fabricated using IDT’s high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.
All bidirectional inputs and outputs of the IDT71256SA are
TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71256SA is packaged in a 28-pin 300 mil Plastic
SOJ, 28-pin 300 mil Plastic Dip, 28-pin 300 mil TSOP Type I
and 28-pin 600 mil Plastic Dip.
FUNCTIONAL BLOCK DIAGRAM
A
0
ADDRESS
DECODER
A
14
262,144 BIT
MEMORY ARRAY
V
CC
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
CONTROL
CIRCUIT
3567 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
JULY 1996
3567/1
1
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
28
27
26
25
24
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output
Current
Com’l.
–0.5 to +7.0
Unit
V
V
CC
WE
V
TERM
(2)
SO28-5
P28-1
P28-2
23
22
21
20
19
18
17
16
15
A
13
A
8
A
9
A
11
OE
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
–55 to +125
–55 to +125
1.0
50
°C
°C
°C
W
mA
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
3567 drw 02
SOJ/DIP
TOP VIEW
OE
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
10
CS
NOTES:
3567 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
A
11
A
9
A
8
A
13
WE
V
CC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
SO28-8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
3567 drw 03
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
11
11
Unit
pF
pF
NOTE:
3567 tbl 03
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
TSOP
TOP VIEW
TRUTH TABLE
(1,2)
CS
OE
WE
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
Function
Read Data
Write Data
Outputs Disabled
Deselected — Standby (I
SB
)
Deselected — Standby (I
SB1
)
3567 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max.
5.5
0
V
CC
+0.5
0.8
Unit
V
V
V
V
L
L
L
H
V
HC
(3)
L
X
H
X
X
H
L
H
X
X
NOTE:
3567 tbl 01
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
–0.2V.
3. Other inputs
≥V
HC
or
≤V
LC
.
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT71256SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= –4mA, V
CC
= Min.
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
3567 tbl 05
2
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5.0V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
–0.2V)
71256SA70
Symbol
I
CC
I
SB
I
SB1
Parameter
Dynamic Operating Current
(2)
CS
≤
V
IL
, Outputs Open, V
CC
= Max., f = f
MAX
Standby Power Supply Current (TTL Level)
(2)
CS
≥
V
IH
, Outputs Open, V
CC
= Max., f = f
MAX
Standby Power Supply Current (CMOS Level)
(2)
CS
≥
V
HC
, Outputs Open, V
CC
= Max., f = 0
V
IN
≤
V
LC
or V
IN
≥
V
HC
Com’l.
130
20
15
Unit
mA
mA
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing .
3567 tbl 06
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
3567 tbl 07
5V
480Ω
DATA
OUT
30pF*
255Ω
3567 drw 04
5V
480Ω
DATA
OUT
5pF*
255Ω
3567 drw 05
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
3
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, CommercialTemperature Range Only)
71256SA70
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ(2)
t
CHZ(2)
t
OE
t
OLZ(2)
t
OHZ(2)
t
OH
t
PU(2)
t
PD(2)
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW(2)
t
WHZ(2)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
Write Cycle Time
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Output Active from End of Write
Write Enable to Output in High-Z
70
—
—
4
0
—
0
0
3
0
—
70
20
20
0
20
0
13
0
4
0
—
70
70
—
11
11
—
10
—
—
25
—
—
—
—
—
—
—
—
—
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3567 tbl 08
Parameter
Min.
Max.
Unit
Write Cycle
NOTES:
1. 0
°
to +70
°
C temperature range only.
2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OLZ
(5)
t
ACS
t
CLZ
DATA
OUT
I
CC
I
SB
(5)
(3)
t
OHZ
t
CHZ
(5)
(5)
HIGH IMPEDANCE
t
PU
DATA
OUT
VALID
t
PD
V
CC
SUPPLY
CURRENT
3567 drw 06
4
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3567 drw 07
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO.1 (
WE
CONTROLLED TIMING)
(1,2,3,5)
t
WC
ADDRESS
t
AW
CS
t
AS
WE
t
WP(3)
t
WR
t
WHZ
DATA
OUT
(4)
(6)
t
OW
HIGH IMPEDANCE
t
DW
t
DH
(6)
t
CHZ
(4)
(6)
DATA
IN
DATA
IN
VALID
3567 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
CS
CONTROLLED TIMING)
(1,2,5)
t
WC
ADDRESS
t
AW
CS
t
AS
WE
t
CW
t
WR
t
DW
DATA
IN
DATA
IN
VALID
t
DH
NOTES:
3567 drw 09
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn
off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified t
WP
.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
±200mV
from steady state.
5
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