3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Revolutionary Pinout
Features
◆
◆
IDT71V124
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM orga-
nized as 128K x 8. It is fabricated using IDT’s high-performance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs. The JEDEC center
power/GND pinout reduces noise generation and improves system
performance.
The IDT71V124 has an output enable pin which operates as fast as
7ns, with address access times as fast as 15ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
The IDT71V124 is packaged in 32-pin 400 mil Plastic SOJ.
◆
◆
◆
◆
◆
◆
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Commercial (0°C to +70°C) and Industrial (–40°C to
+85°C) temperature options
Equal access and cycle times
— Industrial and Commercial: 15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Available in 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A
0
A
16
I/O
0
- I/O
7
O
WE
OE
CS
N N
I
A
T CE
4S NS
R S
12 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
•
•
•
ADDRESS
C
E
•
•
•
1,048,576-BIT
MEMORY ARRAY
DECODER
8
O R
O
F
8
I/O CONTROL
8
CONTROL
LOGIC
3484 drw 01
AUGUST 2000
1
©2000 Integrated Device Technology, Inc.
DSC-3484/05
IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Pin Configuration
A
0
A
1
A
2
A
3
CS
I/O
0
I/O
1
V
DD
GND
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
7
1
32
2
31
3
30
4
29
28
5
6 SO32-3 27
26
7
25
8
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
A
16
A
15
A
14
A
13
OE
I/O
7
I/O
6
GND
V
DD
I/O
5
I/O
4
A
12
A
11
A
10
A
9
A
8
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–0.5 to +4.1
(2)
0 to +70
–55 to +125
–55 to +125
Unit
V
o
o
C
C
C
o
SOJ
Top View
Truth Table
(1,2)
CS
L
L
L
H
V
HC
(3)
OE
L
X
H
X
X
WE
H
L
H
X
X
I/O
DATA
OUT
DATA
IN
High-Z
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
DD
–0.2V.
3. Other inputs
≥V
HC
or
≤
V
LC
.
Capacitance
Symbol
C
IN
C
I/O
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Parameter
(1)
Input Capacitance
I/O Capacitance
O
N N
I
A
T CE
4S NS
R S
12 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
3484 drw 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliabilty.
2. V
TERM
must not exceed V
DD
+ 0.5V.
C
E
0.5
50
W
mA
3484 tbl 02
Function
Read Data
Write Data
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature
GND
0V
V
DD
See Below
See Below
3484 tb l 02a
Output Disabled
Commercial
Industrial
0°C to +70°C
High-Z
Deselected – Standby (I
SB
)
–40°C to +85°C
0V
High-Z
Deselected – Standby (I
SB1
)
3484 tbl 01
Recommended DC Operating
Conditions
Symbol
V
DD
Parameter
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
0
Unit
V
V
V
V
3484 tbl 04
Conditions
V
IN
= 3dV
V
OUT
= 3dV
NOTE:
1. This parameter is guaranteed by device characterization, but is not production
tested.
O R
O
F
Max.
8
8
Unit
pF
Supply Voltage
Ground
GND
V
IH
V
IL
pF
Input High Voltage
Input Low Voltage
2.0
–0.3
(1)
____
____
V
DD
+0.3
0.8
3484 tbl 03
NOTE:
1. V
IL
(min.) = –1V for pulse width less than 5ns, once per cycle.
DC Electrical Characteristics
(V
DD
= 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
IDT71V124
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
DD
= Max., V
IN
= GND to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= GND to V
DD
I
OL
= 8mA, V
DD
= Min.
I
OH
= –8mA, V
DD
= Min.
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3484 tbl 05
2.4
6.42
2
IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(1)
(V
DD
= 3.3V ± 10%, V
LC
= 0.2V, V
HC
= V
DD
– 0.2V)
71V124S15
Symbol
I
CC
I
SB
Parameter
Dynamic Operating Current
CS
< V
IL
, Outputs Open, V
DD
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS
> V
IH
, Outputs Open, V
DD
= Max., f = f
MAX
(2)
Full Standby Power Supply Current (CMOS Level)
CS
> V
HC
, Outputs Open, V
DD
= Max., f = 0
(2)
V
IN
< V
LC
or V
IN
> V
HC
Com'l.
100
35
5
Ind.
120
40
7
71V124S20
Com'l.
95
30
5
Ind.
115
35
7
Unit
mA
mA
mA
I
SB1
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
DATA
OUT
30pF
O
N N
I
A
T CE
4S NS
R S
12 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1 and 2
3484 tbl 07
C
E
3484 tbl 06
3.3V
3.3V
298Ω
216Ω
O R
O
F
3484 drw 03
298Ω
DATA
OUT
5pF*
216Ω
3484 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
6.42
3
IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol
READ CYCLE
t
RC
t
AA
t
ACS
t
CLZ
(1)
t
CHZ
(1)
t
OE
t
OLZ
(1)
t
OHZ
(1)
t
OH
t
PU
(1)
t
PD
(1)
WRITE CYCLE
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
(1)
t
WHZ
(1)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Parameter
(V
DD
= 3.3V ± 10%, Commercial and Industrial Ranges)
71V124S15
Min.
Max.
71V124S20
Min.
Max.
Unit
15
____
____
20
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
____
20
20
____
____
____
3
0
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
Write Cycle Time
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Output Active from End of Write
O
N N
I
A
T CE
4S NS
R S
12 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
____
0
0
C
7
7
____
E
3
0
8
____
8
0
____
5
0
7
4
____
4
0
____
0
____
____
____
15
____
20
15
____
____
20
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3484 tbl 08
12
15
15
0
12
0
____
____
____
____
____
____
____
____
____
____
12
0
15
0
9
0
4
0
Write Enable to Output in High-Z
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
O R
O
F
8
0
____
____
3
0
____
____
5
8
6.42
4
IDT71V124, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit), Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OLZ
(5)
(5)
(3)
t
ACS
t
CLZ
DATA
OUT
V
CC
SUPPLY I
CC
CURRENT I
SB
Timing Waveform of Read Cycle No. 2
(1,2,4)
t
RC
ADDRESS
DATA
OUT
PREVIOUS DATA
OUT
VALID
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
O
N N
I
A
T CE
4S NS
R S
12 IG
A E
V S
P L
71 DE
O
ER W
S
D E
B
R N
t
PU
t
PD
HIGH IMPEDANCE
C
t
CHZ (5)
DATA
OUT
VALID
E
t
OHZ (5)
3484 drw 05
t
AA
t
OH
t
OH
DATA
OUT
VALID
3484 drw 06
O R
O
F
6.42
5
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