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5962R9662802VEC

Description
4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, CDIP16
Categorylogic    logic   
File Size102KB,10 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric View All

5962R9662802VEC Overview

4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, CDIP16

5962R9662802VEC Parametric

Parameter NameAttribute value
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknown
Other featuresOUTPUTS FROM 12 STAGES AVAILABLE; INPUT AC PARAMETRIC VALUES NOT FROM POST RADIATION MEASUREMENT
Counting directionUP
series4000/14000/40000
JESD-30 codeR-CDIP-T16
JESD-609 codee4
Load capacitance (CL)50 pF
Load/preset inputNO
Logic integrated circuit typeBINARY COUNTER
Maximum Frequency@Nom-Sup2200000 Hz
MaximumI(ol)0.00064 A
Operating modeASYNCHRONOUS
Number of digits14
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5/15 V
Prop。Delay @ Nom-Sup486 ns
propagation delay (tpd)486 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum supply voltage (Vsup)18 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose100k Rad(Si) V
Trigger typeNEGATIVE EDGE
minfmax12 MHz
Base Number Matches1
CD4020BMS, CD4024BMS,
CD4040BMS
October 1996
CMOS Ripple-Carry Binary
Counter/Dividers
Pinouts
CD4020BMS
TOP VIEW
Features
• High Voltage Types (20V Rating)
• Medium Speed Operation
• Fully Static Operation
• Buffered Inputs and Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• Common Reset
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25
o
C
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications For Description Of
‘B’ Series CMOS Devices”
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
VSS 8
16 VDD
15 Q11
14 Q10
13 Q8
12 Q9
11 RESET
10
θ
9 Q1
CD4024BMS
TOP VIEW
θ
1
RESET 2
Q7 3
Q6 4
Q5 5
Q4 6
VSS 7
14 VDD
13 NC
12 Q1
11 Q2
10 NC
9 Q3
8 NC
Applications
• Control Counters
• Timers
• Frequency Dividers
• Time-Delay Circuits
Description
NC = NO CONNECTION
CD4020BMS - 14 Stage
CD4024BMS - 7 Stage
CD4040BMS - 12 Stage
CD4020BMS, CD4024BMS, and CD4040BMS are ripple-
carry binary counters. All counter stages are master-slave
flip-flops. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the
RESET line resets the counter to its all zeros state. Schmitt
trigger action on the input-pulse line permits unlimited rise
and fall times. All inputs and outputs are buffered.
The CD4020BMS, CD4024BMS and the CD4040BMS is
supplied in these 14 lead outline packages:
CD4020B
CD4024B
H4Q
H1B
H3W
CD4040B
H4X
H1F
H6W
Q12 1
Q6 2
Q5 3
Q7 4
Q4 5
Q3 6
Q2 7
VSS 8
CD4040BMS
TOP VIEW
16 VDD
15 Q11
14 Q10
13 Q8
12 Q9
11 R
10
θ
9 Q1
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H1F
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3300.1
7-359
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