IDT71V632S6PF8 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> IDT71V632S6PF8

IDT71V632S6PF8: Description64K X 32 CACHE SRAM, 5 ns, PQFP100; Categorystorage; File Size754KB，18 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

Download Datasheet Parametric View All

IDT71V632S6PF8 Overview

64K X 32 CACHE SRAM, 5 ns, PQFP100

IDT71V632S6PF8 Parametric

Parameter Name	Attribute value
maximum clock frequency	100 MHz
Number of functions	1
Number of terminals	100
Minimum operating temperature	0.0 Cel
Maximum operating temperature	70 Cel
Rated supply voltage	3.3 V
Minimum supply/operating voltage	3.14 V
Maximum supply/operating voltage	3.63 V
Processing package description	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
each_compli	Yes
EU RoHS regulations	Yes
state	Active
sub_category	SRAMs
ccess_time_max	5 ns
i_o_type	COMMON
jesd_30_code	R-PQFP-G100
jesd_609_code	e3
storage density	2.10E6 bi
Memory IC type	CACHE SRAM
memory width	32
moisture_sensitivity_level	3
Number of ports	1
Number of digits	65536 words
Number of digits	64K
operating mode	SYNCHRONOUS
organize	64KX32
Output characteristics	3-STATE
Output enable	YES
Packaging Materials	PLASTIC/EPOXY
ckage_code	LQFP
ckage_equivalence_code	QFP100,.63X.87
packaging shape	RECTANGULAR
Package Size	FLATPACK, LOW PROFILE
serial parallel	PARALLEL
eak_reflow_temperature__cel_	260
wer_supplies__v_	3.3
qualification_status	COMMERCIAL
seated_height_max	1.6 mm
standby_current_max	0.0150 Am
standby_voltage_mi	3.14 V
Maximum supply voltage	0.2000 Am
surface mount	YES
Craftsmanship	CMOS
Temperature level	COMMERCIAL
terminal coating	MATTE TIN
Terminal form	GULL WING
Terminal spacing	0.6500 mm
Terminal location	QUAD
ime_peak_reflow_temperature_max__s_	30
length	20 mm
width	14 mm
dditional_feature	ALSO REQUIRES 3.3V I/O SUPPLY

Preview

Download Datasheet

View All

64K x 32

3.3V Synchronous SRAM

Pipelined Outputs

Burst Counter, Single Cycle Deselect

Features

◆

IDT71V632

◆

64K x 32 memory configuration

Supports high system speed:

Commercial:

– A4 4.5ns clock access time (117 MHz)

Commercial and Industrial:

– 5 5ns clock access time (100 MHz)

– 6 6ns clock access time (83 MHz)

– 7 7ns clock access time (66 MHz)

Single-cycle deselect functionality (Compatible with

Micron Part # MT58LC64K32D7LG-XX)

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

Power down controlled by ZZ input

Operates with a single 3.3V power supply (+10/-5%)

Packaged in a JEDEC Standard 100-pin rectangular plastic

thin quad flatpack (TQFP)

Green parts available, see ordering information

Description

Pin Description Summary

–A

BWE

CLK

ADV

ADSC

ADSP

LBO

I/O

–I/O

, V

DDQ

, V

SSQ

Ad d re ss Inp uts

Chip Enab le

Chip s Se le cts

Outp ut Enab le

Glo b al Write Enab le

Byte Write Enab le

Ind ivid ual Byte Write Se le cts

Clo ck

Burst Ad d re ss Ad vance

Ad d re ss Status (Cache Co ntro lle r)

Ad d re ss Status (Pro ce sso r)

Line ar / Inte rle ave d Burst Ord e r

S le e p Mo d e

Data Inp ut/Outp ut

3.3V

Array Gro und , I/O Gro und

The IDT71V632 is a 3.3V high-speed SRAM organized as 64K x 32

with full support of the Pentium™ and PowerPC™ processor interfaces.

The pipelined burst architecture provides cost-effective 3-1-1-1 second-

ary cache performance for processors up to 117MHz.

The IDT71V632 SRAM contains write, data, address, and control

registers. Internal logic allows the SRAM to generate a self-timed write

based upon a decision which can be left until the extreme end of the write

cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V632 can provide four cycles of data for

a single address presented to the SRAM. An internal burst address counter

accepts the first cycle address from the processor, initiating the access

sequence. The first cycle of output data will be pipelined for one cycle before

it is available on the next rising clock edge. If burst mode operation is

selected (ADV=LOW), the subsequent three cycles of output data will be

available to the user on the next three rising clock edges. The order of these

three addresses will be defined by the internal burst counter and the

LBO

input pin.

The IDT71V632 SRAM utilizes IDT's high-performance, high-volume

3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x

20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density

in both desktop and notebook applications.

Inp ut

I/O

Po we r

Synchro no us

Asynchro no us

Synchro no us

N/A

Synchro no us

Asynchro no us

Synchro no us

N/A

3619 tb l 01

Pentium processor is a trademark of Intel Corp.

PowerPC is a trademark of International Business Machines, Inc.

FEBRUARY 2017

DSC-3619/09

Recommended Resources

One of the stage thyristor dimming circuits

Homemade current negative feedback electronic frequency dividing power amplifier 01

Current measurement circuit with a range of 100mA to 1mA

Small indoor induction cordless phone host

Series adjustable voltage stabilizing circuit

Four-tube astable circuit

The reverse withstand voltage peak of the secondary winding rectifier tube D10 reaches -142V. How can I adjust the RCD parameter value to reduce it?: The target value is reduced to about -110V. Figure 1 shows the secondary winding RCD circuit parameters of the auxiliary power supply. The output is 12V, about 5A, the total output power is about 70W,...; 西里古1992 Analog electronics

Electronic keyboard design: Urgent...! Does anyone know the assembly language of a multifunctional electronic keyboard that can realize the eight-tone and music playback functions. It can also select songs and stop. Thanks!...; 青文 MCU

Linear's power chip LT1931A: I wanted to design a -3V output circuit using LT1931A. Why is the -3V output of the out port unstable and fluctuates by about 1V? See the picture for details. Can any experts give me some advice? ! !...; 雨中的银杏叶 Power technology

A New Calculation Model for Common Mode Rejection Ratio of Measurement Amplifier: [i=s]This post was last edited by paulhyde on 2014-9-15 09:34[/i] It may be helpful to those who are choosing instruments :)...; beijingxiaoxues Electronics Design Contest

Linux operating system: I want to learn operating systems by myself, but people around me say that it is difficult to learn by myself and it is better to attend training. Friends, please give me some suggestions! How did you...; zhangdaoyu Talking

About ucos+lwip routine in 107: Ask all STM32 experts! ! I recently want to use STM32107+UCOS+LWIP to complete some tasks. I downloaded a template from the website http://code.google.com/p/lwip-ucos-stm32/, but after debugging, it d...; 历史的天空 stm32/stm8

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components