Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When
LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS
interface levels.
NOTE:
1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
2
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONTROL INPUT FUNCTION TABLE
(1,2)
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK, xCLK
PCLK, xPCLK
CLK, xCLK
PCLK, xPCLK
Q0:Q4
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Outputs
xQ0:xQ4
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
Disabled
xCLK, xPCLK
CLK, PCLK
Enabled
≈
≈
≈
CLK_EN Timing Diagram
CLK_EN
xQ0, xQ1, xQ2, xQ3, xQ4
Q0, Q1, Q2, Q3, Q4
CLOCK INPUT FUNCTION TABLE
(1)
Inputs
CLK or PCLK
0
1
0
1
Biased
(2)
Biased
(2)
xCLK or xPCLK
1
0
Biased
(2)
Biased
(2)
0
1
Q0:Q4
L
H
L
H
H
L
Outputs
xQ0:xQ4
H
L
H
L
L
H
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTES:
1. H = HIGH
L = LOW
2. See Single-Ended Signal diagram under Application Information at the end of this datasheet.
3
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
V
DD
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Min.
3.135
—
Typ.
3.3
—
Max.
3.465
55
Unit
V
mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input Voltage, HIGH
Input Voltage, LOW
Input Current HIGH
Input Current LOW
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
5
150
μA
μA
-0.3
0.8
V
Test Conditions
Min.
2
Typ.
Max.
V
DD
+ 0.3
Unit
V
DC ELECTRICAL CHARACTERISTICS, DIFFERENTIAL
Symbol
V
PP
V
CMR
I
IH
I
IL
Parameter
Peak-to-Peak Input Voltage
Common Mode Input Voltage
(1,2)
Input Current HIGH
Input Current LOW
xCLK
CLK
xCLK
CLK
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
Test Conditions
Min.
0.15
0.5
Typ.
Max.
1.3
V
DD
- 0.85
5
150
μA
Unit
V
V
μA
NOTES:
1. For single-ended applications, the max. input voltage for CLK / xCLK is V
DD
+ 0.3V.
2. Common mode voltage is defined as V
IH
.
DC ELECTRICAL CHARACTERISTICS, LVPECL
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input Current HIGH
Input Current LOW
PCLK
xPCLK
PCLK
xPCLK
Peak-to-Peak Input Voltage
Common Mode Input Voltage
(1,2)
Output Voltage HIGH
(3)
Output Voltage LOW
(3)
Peak-to-Peak Output Voltage Swing
Test Conditions
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-5
-150
0.15
V
EE
+ 1.5
V
DD
- 1.4
V
DD
- 2
0.6
1.3
V
DD
V
DD
- 1
V
DD
- 1.7
0.85
V
V
V
V
V
Min.
Typ.
Max.
150
5
μA
Unit
μA
NOTES:
1. For single-ended applications, the max. input voltage for PCLK / xPCLK is V
DD
+ 0.3V.
2. Common mode voltage is defined as V
IH
.
3. Outputs terminated with 50Ω to V
DD
- 2V.
4
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
All parameters measured at 500MHz unless noted otherwise;
Cycle-to-cycle jitter = jitter on output; the part does not add jitter
Symbol
F
MAX
t
PD
t
SK
(
O
)
t
SK
(
PP
)
t
R
t
F
odc
Parameter
Output Frequency
Propagation Delay
(1)
Output Skew
(2,4)
Part-to-Part Skew
(3,4)
Output Rise Time
Output Fall Time
Output Duty Cycle
20 - 80% @ 50MHz
20 - 80% @ 50MHz
300
300
48
50
f
≤
650MHz
1
Test Conditions
Min.
Typ.
Max.
650
2.1
35
150
700
700
52
Unit
MHz
ns
ps
ps
ps
ps
%
NOTES:
1. Measured from the differential input crossingpoint to the differential output crossingpoint.
2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each
device, the outputs are measured at the differential crosspoints.
4. This parameter is defined in accordance with JEDEC Standard 65.
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