a
FEATURES
Complete, Fully Calibrated Monolithic System
Five Stages, Each Having 10 dB Gain, 350 MHz BW
Direct Coupled Fully Differential Signal Path
Logarithmic Slope, Intercept and AC Response are
Stable Over Full Military Temperature Range
Dual Polarity Current Outputs Scaled 1 mA/Decade
Voltage Slope Options (1 V/Decade, 100 mV/dB, etc.)
Low Power Operation (Typically 220 mW at 5 V)
Low Cost Plastic Packages Also Available
APPLICATIONS
Radar, Sonar, Ultrasonic and Audio Systems
Precision Instrumentation from DC to 120 MHz
Power Measurement with Absolute Calibration
Wide Range High Accuracy Signal Compression
Alternative to Discrete and Hybrid IF Strips
Replaces Several Discrete Log Amp ICs
PRODUCT DESCRIPTION
DC-Coupled Demodulating
120 MHz Logarithmic Amplifier
AD640
signal output at +50 dB (referred to input) is provided to operate
AD640s in cascade.
The logarithmic response is absolutely calibrated to within
±1
dB
for dc or square wave inputs from
±
0.75 mV to
±
200 mV, with
an intercept (logarithmic offset) at 1 mV dc. An integral X10
attenuator provides an alternative input range of
±
7.5 mV to
±
2 V dc. Scaling is also guaranteed for sinusoidal inputs.
The AD640B is specified for the industrial temperature range of
–40°C to +85°C and the AD640T, available processed to MIL-
STD-883B, for the military range of –55°C to +125°C. Both are
available in 20-lead side-brazed ceramic DIPs or leadless chip
carriers (LCC). The AD640J is specified for the commercial
temperature range of 0°C to +70°C, and is available in both
20-lead plastic DIP (N) and PLCC (P) packages.
This device is now available to Standard Military Drawing
(DESC) number 5962-9095501MRA and 5962-9095501M2A.
PRODUCT HIGHLIGHTS
The AD640 is a complete monolithic logarithmic amplifier. A single
AD640 provides up to 50 dB of dynamic range for frequencies
from dc to 120 MHz. Two AD640s in cascade can provide up to
95 dB of dynamic range at reduced bandwidth. The AD640 uses a
successive detection scheme to provide an output current propor-
tional to the logarithm of the input voltage. It is laser calibrated to
close tolerances and maintains high accuracy over the full military
temperature range using supply voltages from
±4.5
V to
±
7.5 V.
The AD640 comprises five cascaded dc-coupled amplifier/limiter
stages, each having a small signal voltage gain of 10 dB and a –3 dB
bandwidth of 350 MHz. Each stage has an associated full-wave
detector, whose output current depends on the absolute value of its
input voltage. The five outputs are summed to provide the video
output (when low-pass filtered) scaled at 1 mA per decade (50
µA
per dB). On chip resistors can be used to convert this output cur-
rent to a voltage with several convenient slope options. A balanced
1. Absolute calibration of a wideband logarithmic amplifier is
unique. The AD640 is a high accuracy measurement device,
not simply a logarithmic building block.
2. Advanced design results in unprecedented stability over the
full military temperature range.
3. The fully differential signal path greatly reduces the risk of
instability due to inadequate power supply decoupling and
shared ground connections, a serious problem with com-
monly used unbalanced designs.
4. Differential interfaces also ensure that the appropriate ground
connection can be chosen for each signal port. They further
increase versatility and simplify applications. The signal input
impedance is ~500 kΩ in shunt with ~2 pF.
5. The dc-coupled signal path eliminates the need for numerous
interstage coupling capacitors and simplifies logarithmic
conversion of subsonic signals.
(continued
on page 4)
FUNCTIONAL BLOCK DIAGRAM
RG1 1k
17
COM 18
ATN OUT
SIG +IN
SIG –IN
ATN LO
ATN COM
ATN COM
19
20
10dB
1
2
27
3
30
4
270
5
ATN IN
6
BL1
GAIN BIAS REGULATOR
7
RG0
16
1k
RG2
15
LOG OUT
14
LOG COM
13
INTERCEPT POSITIONING BIAS
12 +V
S
FULL-WAVE
DETECTOR
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
11 SIG +OUT
10dB
10 SIG –OUT
AMPLIFIER/LIMITER
9 BL2
AMPLIFIER/LIMITER
SLOPE BIAS REGULATOR
8
ITC
–V
S
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD640–SPECIFICATIONS
DC SPECIFICATIONS
(V =
S
5 V, T
A
= +25 C, unless otherwise noted)
Conditions
Min
AD640J
Typ
Max
Min
AD640B
Typ
Max
Min
AD640T
Typ
Max
Units
Model
Parameter
TRANSFER FUNCTION
1
SIGNAL INPUTS (Pins 1, 20)
Input Resistance
Input Offset Voltage
vs. Temperature
Over Temperature
vs. Supply
Input Bias Current
Input Bias Offset
Common-Mode Range
INPUT ATTENUATOR
(Pins 2, 3, 4, 5 and 19)
Attenuation
2
Input Resistance
SIGNAL OUTPUT (Pins 10, 11)
Small Signal Gain
3
Peak Differential Output
4
Output Resistance
Quiescent Output Voltage
LOGARITHMIC OUTPUT
5
(Pin 14)
Voltage Compliance Range
Slope Current, I
Y
Accuracy vs. Temperature
Accuracy vs. Supply
Intercept Voltage
6
, V
X
vs. Temperature
Over Temperature
vs. Supply
Logarithmic Offset
(Alt. Definition of V
X
)
vs. Temperature
Over Temperature
vs. Supply
Intercept Voltage Using Attenuator
Zero Signal Output Current
7
ITC Disabled
Maximum Output Current
APPLICATIONS RESISTORS
(Pins 15, 16, 17)
DC LINEARITY
V
IN
±1
mV to
±
100 mV
TOTAL ABSOLUTE DC
ACCURACY
V
IN
=
±
1 mV to
±100
mV
8
Over Temperature
Over Supply Range
V
IN
=
±
0.75 mV to
±200
mV
Using Attenuator
V
IN
=
±
10 mV to
±
1 V
Over Temperature
V
IN
=
±
7.5 mV to 2 V
POWER REQUIREMENTS
Voltage Supply Range
Quiescent Current
9
+V
S
(Pin 12)
–V
S
(Pin 7)
I
OUT
= I
Y
LOG |V
IN
/V
X
| for V
IN
=
±
0.75 mV to
±
200 mV dc
Differential
Differential
T
MIN
to T
MAX
2
7
1
–2
25
+0.3
–2
2
7
1
25
+0.3
–2
2
7
1
500
50
0.8
500
50
0.8
500
50
0.8
kΩ
µV
µV/°C
µV
µV/V
µA
µA
V
500
200
200
300
25
+0.3
Pin 5 to Pin 19
Pins 5 to 3/4
20
300
50
±180
75
–90
–0.3
0.95
+V
S
–1
1.05
–0.3
0.98
20
300
50
±
180
75
–90
+V
S
–1
1.02
–0.3
0.98
0.98
20
300
50
±
180
75
–90
V
S
–1
1.02
1.02
0.4
1.05
1.10
2
–59.5
–60.5
–60.9
–60.0
0.004
0.017
10.0
–0.2
–0.27
2.3
1.000
0.35
–59.5
–59.1
11.0
dB
Ω
dB
mV
Ω
mV
V
mA
%/°C
mA
%/V
mV
µV/°C
mV
µV/V
dBV
dB/°C
dB
dB/V
mV
mA
mA
mA
kΩ
dB
Either Pin to COM
Either Pin to COM
1.00
0.002
0.08
1.00
0.5
2
1.00
0.002
0.08
1.00
0.5
2
1.00
0.002
0.08
1.00
0.5
T
MIN
to T
MAX
+V
S
= 4.5 V to 7.5 V
0.85
T
MIN
to T
MAX
±V
S
= 4.5 V to 7.5 V
–61.5
T
MIN
to T
MAX
±V
S
= 4.5 V to 7.5 V
8.25
Pin 8 to COM
1.0
1.15
0.95
0.4
1.05
0.95
0.90
–60.0
0.004
0.017
10.0
–0.2
–0.27
2.3
1.000
0.35
–58.7
–60.5
–60.0
0.004
0.017
10.0
–0.2
–0.27
2.3
1.000
0.35
11.75
9.0
11.0
9.0
0.995
1.2
1.005
0.6
0.995
1.005
0.6
0.55
T
MIN
to T
MAX
±V
S
= 4.5 V to 7.5 V
1.0
0.4
0.6
1.2
2
3
2
3
2.5
3
3.5
0.55
1.0
0.4
0.6
1.2
0.9
1.7
1.0
2.0
1.5
2.0
2.5
0.55
1.0
0.4
0.6
1.2
0.9
1.8
1.0
2.0
1.5
2.0
2.5
dB
dB
dB
dB
dB
dB
dB
T
MIN
to T
MAX
4.5
T
MIN
to T
MAX
T
MIN
to T
MAX
9
35
7.5
15
60
4.5
9
35
15
60
7.5
4.5
9
35
15
60
7.5
V
mA
mA
–2–
REV. C
AD640
AC SPECIFICATIONS
(V
Model
Parameter
SIGNAL INPUTS (Pins 1, 20)
Input Capacitance
Noise Spectral Density
Tangential Sensitivity
3 dB BANDWIDTH
Each Stage
All Five Stages
LOGARITHMIC OUTPUTS
5
Slope Current, I
Y
f< = 1 MHz
f = 30 MHz
f = 60 MHz
f = 90 MHz
f = 120 MHz
Intercept, Dual AD640s
10, 11
f< = 1 MHz
f = 30 MHz
f = 60 MHz
f = 90 MHz
f = 120 MHz
AC LINEARITY
–40 dBm to –2 dBm
12
–35 dBm to –10 dBm
12
–75 dBm to 0 dBm
10
–70 dBm to –10 dBm
10
–75 dBm to +15 dBm
13
PACKAGE OPTION
20-Lead Ceramic DIP Package (D)
20-Terminal Ceramic LCC (E)
20-Lead Plastic DIP Package (N)
20-Lead Plastic Leaded Chip Carrier (P)
NUMBER OF TRANSISTORS
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 10 kHz
S
=
5 V, T
A
= +25 C, unless otherwise noted)
Conditions
Either Pin to COM
1 kHz to 10 MHz
BW = 100 MHz
Min
AD640J
Typ
2
2
–72
350
145
Max
Min
AD640B
Typ
2
2
–72
350
145
Max
Min
AD640T
Typ
2
2
–72
350
145
Max
Units
pF
nV/√Hz
dBm
MHz
MHz
Pins 1 & 20 to 10 & 11
0.96
0.88
0.82
1.0
0.94
0.90
0.88
0.85
–88.6
–87.6
–86.3
–83.9
–80.3
0.5
0.25
0.75
0.5
0.5
1.04
1.00
0.98
0.98
0.91
0.86
1.0
0.94
0.90
0.88
0.85
–88.6
–87.6
–86.3
–83.9
–80.3
0.5
0.25
0.75
0.5
0.5
AD640BD
AD640BE
1.02
0.97
0.94
0.98
0.91
0.86
1.0
0.94
0.90
0.88
0.85
–88.6
–87.6
–86.3
–83.9
–80.3
0.5
0.25
0.75
0.5
0.5
AD640TD
AD640TE
1.02
0.97
0.94
mA
mA
mA
mA
mA
dBm
dBm
dBm
dBm
dBm
dB
dB
dB
dB
dB
–90.6
–86.6
–89.6
–87.6
–89.6
–87.6
2.0
1.0
3.0
2.0
3.0
1.0
0.5
1.5
1.0
1.5
1.0
0.5
1.5
1.0
1.5
AD640]N
AD640JP
155
AD640BP
155
155
NOTES
1
Logarithms to base 10 are used throughout. The response is independent of the sign of V
IN
.
2
Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/
°C.
3
Overall gain is trimmed using a
±
200
µV
square wave at 2 kHz, corrected for the onset of compression.
4
The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.
5
Currents defined as flowing
into
Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured
by linear regression over central region of transfer function.
6
The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG
10
(V
X
/1 V).
7
The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.
8
Operating in circuit of Figure 24 using
±
0.1% accurate values for R
LA
and R
LB.
Includes slope and nonlinearity errors. Input offset errors also included for
V
IN
>3 mV dc, and over the full input range in ac applications.
9
Essentially independent of supply voltages.
10
Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50
Ω
= 223 mV rms.
11
For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept
for dual AD640 system.
12
Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50
Ω
= 223 mV rms.
13
Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.
All min and max specifications are guaranteed, but only those in
boldface
are 100% tested on all production units. Results from those tests are used to calculate
outgoing quality levels.
Specifications subject to change without notice.
THERMAL CHARACTERISTICS
JC
( C/W)
JA
( C/W)
20-Lead Ceramic DIP Package (D-20)
20-Terminal Ceramic LCC (E-20A)
20-Lead Plastic DIP Package (N-20)
20-Lead Plastic Leaded Chip Carrier (P-20A)
25
25
24
28
85
85
61
75
REV. C
–3–
AD640
(continued
from page 1)
ABSOLUTE MAXIMUM RATINGS*
6. The low input offset voltage of 50
µV
(200
µV
max) ensures
good accuracy for low level dc inputs.
7. Thermal recovery “tails,” which can obscure the response
when a small signal immediately follows a high level input,
have been minimized by special attention to design details.
8. The noise spectral density of 2 nV/√Hz results in a noise floor of
~23
µV
rms (–80 dBm) at a bandwidth of 100 MHz. The dy-
namic range using cascaded AD640s can be extended to 95 dB
by the inclusion of a simple filter between the two devices.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
7.5 V
Input Voltage (Pin 1 or Pin 20 to COM) . . . . –3 V to +300 mV
Attenuator Input Voltage (Pin 5 to Pin 3/4) . . . . . . . . . . .
±
4 V
Storage Temperature Range D, E . . . . . . . . . –65°C to +150°C
Storage Temperature Range N, P . . . . . . . . . –65°C to +125°C
Ambient Temperature Range, Rated Performance
Industrial, AD640B . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Military, AD640T . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Commercial, AD640J . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CHIP DIMENSIONS AND
BONDING DIAGRAM
Dimensions shown in inches and (mm).
ORDERING GUIDE
Model
AD640JN
AD640JP
AD640BD
AD640BE
AD640BP
AD640TD/883B
5962-9095501MRA
AD640TE/883B
Temperature
Range
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Package
Description
20-Lead Plastic DIP
20-Lead PLCC
20-Lead Ceramic DIP
20-Terminal Ceramic
LCC
20-Lead PLCC
20-Lead Ceramic DIP
20-Lead Ceramic DIP
20-Terminal Ceramic
LCC
20-Terminal Ceramic
LCC
Die
Evaluation Board
13" Tape and Reel
7" Tape and Reel
Package
Option
N-20
P-20A
D-20
E-20A
P-20A
D-20
D-20
E-20A
E-20A
5962-9095501M2A –55°C to +125°C
AD640TCHIPS
AD640EB
AD640JP-REEL
AD640JP-REEL7
–55°C to +125°C
0°C to +70°C
0°C to +70°C
P-20A
P-20A
CONNECTION DIAGRAMS
20-Lead Ceramic DIP (D) Package
20-Lead Plastic DIP (N) Package
20-Lead PLCC (P) Package
20-Terminal Ceramic LCC (E) Package
ATN COM
ATN COM
ATN OUT
ATN LO
SIG –IN
1
ATN LO
2
ATN COM
3
ATN COM
4
ATN IN
5
BL1
6
20
SIG +IN
19
ATN OUT
18
CKT COM
17
RG1
SIG +IN
SIG –IN
3
2
1
20
19
18
CKT COM
17
RG1
16
RG0
15
RG2
14
LOG OUT
3
2
1
20 19
ATN COM
4
ATN IN
5
BL1
6
–V
S 7
ITC
8
9
10
ATN OUT
18
CKT COM
17
RG1
16
RG0
15
RG2
14
LOG OUT
ATN LO
PIN 1
IDENTIFIER
ATN COM
4
ATN IN
5
BL1
6
–V
S
7
AD640
16
RG0
AD640
TOP VIEW
(Not to Scale)
AD640
TOP VIEW
(Not to Scale)
TOP VIEW
15
RG2
(Not to Scale)
14
LOG OUT
–V
S 7
ITC
8
13
LOG COM
12
+V
S
11
SIG +OUT
ITC
8
9
10 11 12 13
11
12
13
BL2
SIG –OUT
SIG –OUT
10
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD640 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
LOG COM
SIG +OUT
+V
S
BL2
9
LOG COM
BL2
SIG –OUT
SIG +OUT
+V
S
SIG +IN
SIG –IN
REV. C
Typical DC Performance Characteristics–AD640
1.015
1.010
SLOPE CURRENT – mA
1.005
1
0.995
0.990
0.985
0.980
–60 –40 –20
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
–60 –40 –20
SLOPE CURRENT – mA
0 20 40 60 80 100 120 140
TEMPERATURE – C
1.006
1.004
1.002
1.000
0.998
0.996
0.994
4.5
INTERCEPT – mV
0 20 40 60 80 100 120 140
TEMPERATURE – C
5.0
5.5
6.0
6.5
7.0
7.5
POWER SUPPLY VOLTAGES – Volts
Figure 1. Slope Current, I
Y
vs.
Temperature
Figure 2. Intercept Voltage, V
X
, vs.
Temperature
Figure 3. Slope Current, I
Y
vs.
Supply Voltages
1.015
1.010
1.005
INTERCEPT – mV
DEVIATION OF INPUT OFFSET VOLTAGE – mV
14
13
12
11
10
9
8
7
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – C
+0.4
+0.3
+0.2
+0.1
0
–0.1
–0.2
–0.3
–60 –40 –20
INPUT OFFSET VOLTAGE
DEVIATION WILL BE WITHIN
SHADED AREA.
INTERCEPT VOLTAGE – mV
1.000
0.995
0.990
0.985
4.5
5.0
5.5
6.0
6.5
7.0
7.5
POWER SUPPLY VOLTAGES – Volts
0 20 40 60 80 100 120 140
TEMPERATURE – C
Figure 4. Intercept Voltage, V
X
, vs.
Supply Voltages
Figure 5. Intercept Voltage (Using
Attenuator) vs. Temperature
Figure 6. Input Offset Voltage
Deviation vs. Temperature
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0.1
ERROR – dB
2
1
0
2.5
2.5
OUTPUT CURRENT – mA
ABSOLUTE ERROR – dB
1.5
ABSOLUTE ERROR – dB
0 20 40 60 80 100 120 140
TEMPERATURE – C
2.0
2.0
1.5
1.0
1.0
0.5
0.5
1.0
10.0
100.0
INPUT VOLTAGE – mV
(EITHER SIGN)
1000.0
0
–60 –40 –20
0
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – C
Figure 7. DC Logarithmic Transfer
Function and Error Curve for Single
AD640
Figure 8. Absolute Error vs. Tem-
perature, V
IN
= 1 mV to 100 mV
Figure 9. Absolute Error vs.
Temperature, Using Attenuator.
V
IN
= 10 mV to 1 V, Pin 8
Grounded to Disable ITC Bias
REV. C
–5–
Talking
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