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844004BGI-01

Description
Clock Generator, 156.25MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size1MB,16 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

844004BGI-01 Overview

Clock Generator, 156.25MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24

844004BGI-01 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instruction4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Contacts24
Reach Compliance Codenot_compliant
ECCN codeEAR99
Other featuresALSO OPERATES AT 3.3V SUPPLY
JESD-30 codeR-PDSO-G24
JESD-609 codee0
length7.8 mm
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency156.25 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
power supply2.5/3.3 V
Master clock/crystal nominal frequency27.2 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate64 mA
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
FemtoClock
®
Crystal-to-LVDS
Frequency Synthesizer
NRND – Not Recommend for New Designs
ICS844004I-01
NRND
DATA SHEET
General Description
The ICS844004I-01 is a 4 output LVDS Synthesizer optimized to
generate Ethernet reference clock frequencies. Using a 25MHz
18pF parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
156.25MHz, 125MHz and 62.5MHz. The ICS844004I-01 uses IDT’s
3
rd
generation low phase noise VCO technology and can achieve
<1ps typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844004I-01 is packaged in a small 24-pin
TSSOP package.
Features
Four LVDS output pairs
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
Supports the following output frequencies: 156.25MHz, 125MHz,
62.5MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Not Recommended For New Designs
Frequency Select Function Table
Inputs
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
M Div. Value
25
25
25
25
N Div. Value
4
5
10
not used
M/N Div. Value
6.25
5
2.5
Output Frequency (MHz),
(25MHz Ref.)
156.25 (default)
125
62.5
not used
Block Diagram
F_SEL[1:0]
nPLL_SEL
Pulldown
Pulldown
Pin Assignment
2
Q0
nQ1
Q1
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
F_SEL1
REF_CLK
Pulldown
1
1
XTAL_IN
XTAL_OUT
nXTAL_SEL
25MHz
OSC
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
F_SEL[1:0]
0 0 ÷4 (default)
0 1 ÷5
1 0 ÷10
1 1 not used
nQ0
Q1
nQ1
0
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
DDO
Q3
nQ3
GND
nc
nXTAL_SEL
REF_CLK
GND
XTAL_IN
XTAL_OUT
Pulldown
M = 25 (fixed)
Q3
nQ3
MR
Pulldown
ICS844004I-01
24-Lead TSSOP
4.4mm x 7.8mm x 0.92mm
package body
G Package
Top View
ICS844004BGI-01 REVISION A MAY 20, 2013
1
©2013 Integrated Device Technology, Inc.

844004BGI-01 Related Products

844004BGI-01 844004BGI-01T
Description Clock Generator, 156.25MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 Clock Generator, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP
package instruction 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
Contacts 24 24
Reach Compliance Code not_compliant not_compliant
ECCN code EAR99 EAR99
Other features ALSO OPERATES AT 3.3V SUPPLY ALSO OPERATES AT 3.3V SUPPLY
JESD-30 code R-PDSO-G24 R-PDSO-G24
JESD-609 code e0 e0
length 7.8 mm 7.8 mm
Number of terminals 24 24
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP24,.25 TSSOP24,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 225 225
power supply 2.5/3.3 V 2.5/3.3 V
Master clock/crystal nominal frequency 27.2 MHz 27.2 MHz
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm
Maximum slew rate 64 mA 64 mA
Maximum supply voltage 2.625 V 2.625 V
Minimum supply voltage 2.375 V 2.375 V
Nominal supply voltage 2.5 V 2.5 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface TIN LEAD TIN LEAD
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 4.4 mm 4.4 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
Base Number Matches 1 1
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