CMOS ASYNCHRONOUS FIFO WITH
RETRANSMIT
1K x 9, 2K x 9, 4K x 9
Integrated Device Technology, Inc.
IDT72021
IDT72031
IDT72041
FEATURES:
• First-In/First-Out Dual-Port memory
• Bit organization
– IDT72021—1K x 9
– IDT72031—2K x 9
– IDT72041—4K x 9
• Ultra high speed
– IDT72021—25ns access time
– IDT72031—35ns access time
– IDT72041—35ns access time
• Easily expandable in word depth and/or width
• Asynchronous and simultaneous read and write
• Functionally equivalent to IDT7202/03/04 with Output
Enable (
OE
) and Almost Empty/Almost Full Flag (
AEF
)
• Four status flags: Full, Empty, Half-Full (single device
mode), and Almost Empty/Almost Full (7/8 empty or 7/8
full in single device mode)
• Output Enable controls the data output port
• Auto-retransmit capability
• Available in 32-pin DIP and PLCC
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40
o
C to +85
o
C) is avail
able, tested to military electrical specifications
DESCRIPTION:
IDT72021/031/041s are high-speed, low-power, dual-port
memory devices commonly known as FIFOs (First-In/First-
Out). Data can be written into and read from the memory at
independent rates. The order of information stored and ex-
tracted does not change, but the rate of data entering the FIFO
might be different than the rate leaving the FIFO. Unlike a
Static RAM, no address information is required because the
read and write pointers advance sequentially. The IDT72021/
031/041s can perform asynchronous and simultaneous read
and write operations. There are four status flags, (
HF
,
FF
,
EF
,
AEF
) to monitor data overflow and underflow. Output Enable
(
OE
) is provided to control the flow of data through the output
port. Additional key features are Write (
W
), Read (
R
), Retrans-
mit (
RT
), First Load (
FL
), Expansion In (
XI
) and Expansion Out
(
XO
). The IDT72021/031/041s are designed for those appli-
cations requiring data control flags and Output Enable (
OE
) in
multiprocessing and rate buffer applications.
The IDT72021/031/041s are fabricated using IDT’s CMOS
technology. Military grade product is manufactured in compli-
ance with the latest version of MIL-STD-883, Class B, for high
reliability systems.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUT
(D
0
–D
8
)
W
WRITE
CONTROL
1
2
WRITE
POINTER
1024/
2048/
4096
THREE-
STATE
BUFFERS
RAM
ARRAY
1024 x 9
2048 x 9
4096 x 9
READ
POINTER
OE
RESET
LOGIC
RS
FL/RT
R
READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
DATA OUTPUTS
(Q
0
–Q
8
)
EF
FF
AEF
XI
XO/HF
2677 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2677/7
5.09
1
IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
V
CC
D
3
D
8
D
5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D32-1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
D
4
D
5
D
6
D
7
W
INDEX
V
CC
D
4
W
D
8
D
3
D
2
4 3 2
D
2
D
1
D
0
5
6
7
8
9
10
11
12
13
1
32 31 30
29
28
27
26
25
24
23
22
21
D
6
D
7
D
1
D
0
XI
AEF
FF
Q
0
Q
1
Q
2
J32-1
FL
/
RT
RS
OE
EF
XO
/
HF
Q
7
Q
6
XI
AEF
FF
Q
0
Q
1
Q
2
Q
3
Q
8
FL
/
RT
RS
OE
EF
XO
/
HF
Q
7
Q
6
Q
5
Q
4
14 15 16 17 18 19 20
R
GND
2677 drw 02
Q
3
Q
8
GND
GND
Q
4
Q
5
R
GND
2677 drw 03
PLCC TOP VIEW
DIP TOP VIEW
PIN DESCRIPTIONS
Symbol
D
0
–D
8
Name
Inputs
Reset
I/O
I
I
Data inputs for 9-bit wide data.
When
RS
is set LOW, internal READ and WRITE pointers are set to the first location of the RAM
array.
HF
and
FF
go HIGH, and
AEF
and
EF
go LOW. A reset is required before an initial WRITE
after power-up.
R
and
W
must be HIGH during
RS
cycle.
When WRITE is LOW, data can be written into the RAM array sequentially, independent of
READ. In order for WRITE to be active,
FF
must be HIGH. When the FIFO is full (
FF
-LOW),
the internal WRITE operation is blocked.
When READ is LOW, data can be read from the RAM array sequentially, independent of
WRITE. In order for READ to be active,
EF
must be HIGH. When the FIFO is empty (
EF
-LOW),
the internal READ operation is blocked. The three-state output buffer is controlled by the read
signal and the external output control
(OE
).
Description
RS
W
R
FL
/
RT
Write
I
Read
I
First Load/
Retransmit
I
This is a dual-purpose input. In the single device configuration (
XI
grounded), activating
retransmit (
FL
/
RT
-LOW) will set the internal READ pointer to the first location. There is no effect
on the WRITE pointer.
R
and
W
must be HIGH before setting
FL
/
RT
LOW. Retransmit is not
compatible with depth expansion. In the depth expansion configuration,
FL
/
RT
-LOW indicates
the first activated device.
XI
OE
Expansion In
Output Enable
I
I
In the single device configuration,
XI
is grounded. In depth expansion or daisy chain expansion,
XI
is connected to
XO
(expansion out) of the previous device.
When
OE
is set HIGH, the data flow through the three-state output buffer is inhibited regardless
of an active READ operation. A read operation does increment the read pointer in this situation.
When
OE
is set LOW, Q
0
-Q
8
are still in a HIGH impedance condition if no READ occurs. For
a complete READ operation with data appearing on Q
0
-Q
8
, both
R
and
OE
should be asserted
LOW.
When
FF
goes LOW, the device is full and further WRITE operations are inhibited. When
FF
is HIGH, the device is not full.
When
EF
goes LOW, the device is empty and further READ operations are inhibited. When
EF
is HIGH, the device is not empty.
When
AEF
is LOW, the device is empty to 1/8 full or 7/8 to completely full. When
AEF
is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
This is a dual purpose output. In the single device configuration (
XI
grounded), the device is
more than half full when
HF
is LOW. In the depth expansion configuration (
XO
connected to
XI
of the next device), a pulse is sent from
XO
to
XI
when the last location in the RAM array is
filled.
Data outputs for 9-bit wide data.
2677 tbl 01
FF
EF
AEF
XO
/
HF
Full Flag
Empty Flag
Almost-Empty/
Almost-Full Flag
Expansion Out/
Half-Full Flag
O
O
O
O
Q
0
–Q
8
Outputs
O
5.09
2
IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATUS FLAG
Number of Words in FIFO
1K
0
1-127
128-512
513-896
897-1023
1024
2K
0
1-255
256-1024
1025-1792
1793-2047
2048
4K
0
1-511
512-2048
2049-3584
3585-4095
4096
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
FF AEF HF
H
H
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
EF
L
H
H
H
H
H
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Condition
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
2677 tbl 03
NOTE:
1. These parameters are sampled and not 100% tested.
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CCM
Parameter
Military Supply
Voltage
Commercial
Supply Voltage
Supply Voltage
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial and
Military
Min.
4.5
4.5
0
2.0
2.2
—
Typ.
5.0
5.0
0
—
—
—
Max.
5.5
5.5
0
—
—
0.8
Unit
V
V
V
V
V
V
2677 tbl l 02
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
V
TERM
Terminal Voltage
with Respect
to GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
I
OUT
DC Output
Current
(1)
Com’l.
Mil.
Unit
–0.5 to +7.0 –0.5 to +7.0 V
V
CCC
GND
V
IH
0 to +70
–55 to +125
°C
°C
°C
mA
V
IH
V
IL(1)
–55 to +125 –65 to +135
–55 to +125 –65 to +155
50
50
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2677 tbl 05
NOTE:
2677 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.
5.09
3
IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS — IDT72021
(Commercial: V
CC
= 5.0V±10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V±10%, T
A
= –55°C to +125°C)
IDT72021
Commercial
t
A
=25,35ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3,4)
I
CC2(3)
I
CC3(3)
Parameter
Input Leakage Current
(Any Input)
Output Leakage Current
Output Logic “1” Voltage
I
OH
= –2mA
Output Logic “0” Voltage
I
OL
= 8mA
Active Power Supply
Current
Standby Current
(
R
=
W
=
RS
=
FL
/
RT
= V
IH
)
Power Down Current
(All Input = V
CC
– 0.2V)
Min.
–1
–10
2.4
—
—
—
—
Typ.
—
—
—
—
—
—
—
Max.
1
10
—
0.4
120
12
500
IDT72021
Military
t
A
=30,40ns
Min.
–10
–10
2.4
—
—
—
—
Typ.
—
—
—
—
—
—
—
Max.
10
10
—
0.4
140
20
900
–1
–10
2.4
—
—
—
—
IDT72021
Commercial
t
A
=50ns
Min.
Typ.
—
—
—
—
50
5
—
Max.
1
10
—
0.4
80
8
500
–10
–10
2.4
—
—
—
—
IDT72021
Military
t
A
=50ns
Min.
Typ. Max.
—
—
—
—
70
8
—
10
10
—
0.4
100
15
900
Unit
µA
µA
V
V
mA
mA
µA
2677 tbl 06
DC ELECTRICAL CHARACTERISTICS — IDT72031, IDT72041
(Commercial: V
CC
= 5.0V±10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V±10%, T
A
= –55°C to +125°C)
IDT72031
IDT72041
Commercial
t
A
=35,50ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3,5)
I
CC2(3)
I
CC3(3)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage I
OUT
= –2mA
Output Logic “0” Voltage I
OUT
= 8mA
Active Power Supply Current
Standby Current (
R
=
W
=
RS
=
FL
/
RT
= V
IH
)
Power Down Current (All Input = V
CC
– 0.2V)
Min.
–1
–10
2.4
—
—
—
—
Typ.
—
—
—
—
75
8
—
Max.
1
10
—
0.4
120
12
2
IDT72031
IDT72041
Military
t
A
=40,50ns
Min.
–10
–10
2.4
—
—
—
—
Typ. Max. Unit
—
—
—
—
100
12
—
10
10
—
0.4
150
25
4
µA
µA
V
V
mA
mA
mA
2677 tbl 07
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
R
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
3. I
CC
measurements are made with
OE
= HIGH.
4. Tested at f = 20MHz.
5. Tested at f = 15.3 MHz.
5.09
4
IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS — IDT72021
(1)
(Commercial: V
CC
= 5.0V±10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V±10%, T
A
= –55°C to +125°C)
Com’l
72021L25
Symbol
f
S
t
RC
t
A
t
RR
t
RPW
t
RLZ
t
WLZ
t
DV
t
RHZ
t
WC
t
WPW
t
WR
t
DS
t
DH
t
RSC
t
RS
t
RSS
t
RSR
t
RTC
t
RT
t
RTR
t
RSF1
t
RSF2
t
REF
t
RFF
t
RPE
t
WEF
t
WFF
t
WHF
t
RHF
t
WPF
t
RF
t
WF
t
OEHZ
t
OELZ
t
AOE
Parameter
Shift Frequency
Min. Max.
—
35
—
10
25
5
5
5
—
35
25
10
15
0
35
25
25
10
35
25
10
—
—
—
—
25
—
—
—
—
25
—
—
0
0
—
28.5
—
25
—
—
—
—
—
18
—
—
—
—
—
—
—
—
—
—
—
—
35
35
25
25
—
25
25
35
35
—
35
35
12
12
15
Mil.
72021L30
Min.
—
40
—
10
30
5
5
5
—
40
30
10
18
0
40
30
30
10
40
30
10
—
—
—
—
30
—
—
—
—
30
—
—
0
0
—
Max.
25
—
30
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
40
40
30
30
—
30
30
40
40
—
40
40
15
15
18
Com’l
72021L35
Min.
—
45
—
10
35
5
5
5
—
45
35
10
18
0
45
35
35
10
45
35
10
—
—
—
—
35
—
—
—
—
35
—
—
0
0
—
Max.
22.2
—
35
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
—
45
45
30
30
—
30
30
45
45
—
45
45
17
17
20
Mil.
72021L40
Min.
—
50
—
10
40
5
5
5
—
50
40
10
20
0
50
40
40
10
50
40
10
—
—
—
—
40
—
—
—
—
40
—
—
0
0
—
Max.
20
—
40
—
—
—
—
—
25
—
—
—
—
—
—
—
—
—
—
—
—
50
50
35
35
—
35
35
50
50
—
50
50
20
20
25
Com’l & Mil.
72021L50
Min. Max. Unit
—
65
—
15
50
10
5
5
—
65
50
15
30
5
65
50
50
15
65
50
15
—
—
—
—
50
—
—
—
—
50
—
—
0
0
—
15
—
50
—
—
—
—
—
30
—
—
—
—
—
—
—
—
—
—
—
—
65
65
45
45
—
45
45
65
65
—
65
65
25
25
30
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2677 tbl 08
R
Cycle Time
Access Time
R
Recovery Time
R
Pulse Width
(2)
R
Pulse LOW to Data Bus at Low-Z
(3)
W
Pulse HIGH to Data Bus at Low-Z
(3,4)
Data Valid from
R
Pulse HIGH
R
Pulse HIGH to Data Bus at High-Z
(3)
W
Cycle Time
W
Pulse Width
(2)
W
Recovery Time
Data Set-up Time
Data Hold Time
RS
Cycle Time
RS
Pulse Width
(2)
RS
Set-up Time
RS
Recovery Time
RT
Cycle Time
RT
Pulse Width
(2)
RT
Recovery Time
RS
to
EF
and
AEF
LOW
RS
to
HF
and
FF
HIGH
R
LOW to
EF
LOW
R
HIGH to
FF
HIGH
R
Pulse Width After
EF
HIGH
W
HIGH to
EF
HIGH
W
LOW to
EF
LOW
W
LOW to
HF
LOW
R
HIGH to
HF
HIGH
W
Pulse Width after
FF
HIGH
R
HIGH to Transitioning
AEF
W
LOW to Transitioning
AEF
OE
HIGH to High-Z (Disable)
(3)
OE
LOW to Low-Z (Enable)
(3)
OE
LOW Data Valid (Q
0
–Q
8
)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5.09
5
Embedded System
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