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ISL5957
Data Sheet
November 12, 2004
FN6080.1
14-Bit, +3.3V, 260+MSPS, High Speed D/A
Converter
The ISL5957 is a 14-bit, 260+MSPS (Mega Samples Per
Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in high
performance communication systems such as base
transceiver stations utilizing 2.5G or 3G cellular protocols.
This device complements the ISL5x57 family of high speed
converters, which include 10, 12, and 14-bit devices.
Features
• Low Power . . . . . 103mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(75dBc to Nyquist, f
S
= 130MSPS, f
OUT
= 10MHz)
• UMTS Adjacent Channel Power =71dB at 19.2MHz
• EDGE/GSM SFDR = 94dBc at 11MHz in 20MHz Window
Ordering Information
PART
NUMBER
ISL5957IB
ISL5957IBZ
(See Note)
ISL5957IA
ISL5957IAZ
(See Note)
ISL5957EVAL1
TEMP.
RANGE
(°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
25
PACKAGE
28 Ld SOIC
28 Ld SOIC
(Pb-free)
PKG.
DWG. #
M28.3
M28.3
CLOCK
SPEED
260MHz
260MHz
• Pin compatible, 3.3V, Lower Power Replacement For The
AD9754 and HI5960
• Pb-Free Available (RoHS Compliant)
Applications
• Cellular Infrastructure - Single or Multi-Carrier: IS-136,
IS-95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
• BWA Infrastructure
• Medical/Test Instrumentation
• Wireless Communication Systems
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
28 Ld TSSOP M28.173 260MHz
28 Ld TSSOP M28.173 260MHz
(Pb-free)
SOIC Evaluation Platform 260MHz
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Pinout
ISL5957
TOP VIEW
D13 (MSB) 1
D12 2
D11 3
D10 4
D9 5
D8 6
D7 7
D6 8
D5 9
D4 10
D3 11
D2 12
D1 13
D0 (LSB) 14
28 CLK
27 DV
DD
26 DCOM
25 NC
24 AV
DD
23 COMP
22 IOUTA
21 IOUTB
20 ACOM
19 NC
18 FSADJ
17 REFIO
16 REFLO
15 SLEEP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL5957
Typical Applications Circuit
ISL5957
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13 (1)
D12 (2)
D11 (3)
D10 (4)
D9 (5)
D8 (6)
D7 (7)
D6 (8)
D5 (9)
D4 (10)
D3 (11)
D2 (12)
D1 (13)
D0 (LSB) (14)
CLK (28)
50Ω
BEAD
+
10µF
10µH
0.1µF
DV
DD
(27)
DCOM (26)
(20) ACOM
(24) AV
DD
(23) COMP
0.1µF
FERRITE
BEAD
10µH
0.1µF
10µF
+
+3.3V (V
DD
)
(21) IOUTB
1:1, Z1:Z2
(22) IOUTA
50Ω
(50Ω)
REPRESENTS
ANY 50Ω LOAD
(18) FSADJ
R
SET
1.91kΩ
(25, 19) NC
(15) SLEEP
(16) REFLO
(17) REFIO
0.1µF
ONE CONNECTION
DCOM
ACOM
Functional Block Diagram
IOUTA
IOUTB
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
INPUT
LATCH
SWITCH
MATRIX
40
CASCODE
CURRENT
SOURCE
40
9 LSBs
+
31 MSB
SEGMENTS
D10
D11
D12
(MSB) D13
UPPER
5-BIT
DECODER
COMP
CLK
INT/EXT
VOLTAGE
REFERENCE
BIAS
GENERATION
REFLO REFIO
FSADJ
SLEEP
2
FN6080.1
November 12, 2004
ISL5957
Pin Descriptions
PIN NO.
1-14
15
16
17
18
19, 25
21
22
23
24
20
26
27
28
PIN NAME
D13 (MSB) Through
D0 (LSB)
SLEEP
REFLO
REFIO
FSADJ
NC
IOUTB
IOUTA
COMP
AV
DD
ACOM
DCOM
DV
DD
CLK
DESCRIPTION
Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20µA active pulldown current.
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable internal
reference.
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.1µF cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x V
FSADJ
/R
SET
.
No Connect. These should be grounded, but can be left disconnected.
The complementary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
Connect 0.1µF capacitor to ACOM.
Analog Supply (+2.7V to +3.6V).
Connect to Analog Ground.
Connect to Digital Ground.
Digital Supply (+2.7V to +3.6V).
Clock Input.
3
FN6080.1
November 12, 2004
ISL5957
Absolute Maximum Ratings
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AV
DD
to ACOM. . . . . . . . . . . . . . . . . . +3.6V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DV
DD
+ 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Offset Drift Coefficient
Full Scale Gain Error, FSE
AV
DD
= DV
DD
= +3.3V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
°C
for All Typical Values
T
A
= -40°C TO 85°C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
14
“Best Fit” Straight Line (Note 8)
(Note 8)
IOUTA (Note 8)
(Note 8)
With External Reference (Notes 2, 8)
With Internal Reference (Notes 2, 8)
-5
-3
-0.006
-
-3
-3
-
-
2
(Note 3)
-1.0
-
±2.5
±1.5
-
+5
+3
+0.006
Bits
LSB
LSB
% FSR
ppm
FSR/°C
% FSR
% FSR
ppm
FSR/°C
ppm
FSR/°C
mA
V
0.1
±0.5
±0.5
±50
±100
-
-
-
+3
+3
-
-
20
1.25
Full Scale Gain Drift
With External Reference (Note 8)
With Internal Reference (Note 8)
Full Scale Output Current, I
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
IOUTFS = 20mA
IOUTFS = 2mA
Full Scale Step
Full Scale Step
260
-
-
-
-
-
300
1.5
1.5
10
50
30
-
-
-
-
-
-
MHz
ns
ns
pF
pA/√Hz
pA/√Hz
AC CHARACTERISTICS
(Using Figure 13 with R
DIFF
= 50Ω and R
LOAD
= 50Ω, Full Scale Output = -2.5dBm)
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 210MSPS, f
OUT
= 80.8MHz, 30MHz Span (Notes 4, 8)
f
CLK
= 210MSPS, f
OUT
= 40.4MHz, 30MHz Span (Notes 4, 8)
f
CLK
= 130MSPS, f
OUT
= 20.2MHz, 20MHz Span (Notes 4, 8)
-
-
-
73
82
86
-
-
-
dBc
dBc
dBc
4
FN6080.1
November 12, 2004
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