598BCA000107DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 598BCA000107DG

598BCA000107DG: DescriptionVideo Clock Generator, 525MHz, CMOS, 5 X 7 MM, ROHS COMPLIANT PACKAGE-8; CategoryThe embedded processor and controller Microcontrollers and processors; File Size550KB，27 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

598BCA000107DG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	598BCA000107DG	-	-	View	Buy Now

598BCA000107DG Overview

Video Clock Generator, 525MHz, CMOS, 5 X 7 MM, ROHS COMPLIANT PACKAGE-8

598BCA000107DG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFN
package instruction	QCCN,
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-XQCC-N8
length	7 mm
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	525 MHz
Package body material	UNSPECIFIED
encapsulated code	QCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	2.54 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, VIDEO
Base Number Matches	1

Preview

Download Datasheet

View All

Si 5 9 8 / S i 5 9 9

10–810 M H

C P

ROGRAMMABLE

XO/VCXO

Features



C programmable output

frequencies from 10 to 810 MHz

0.5 ps RMS phase jitter

Superior power supply rejection:

0.3–0.4 ps additive jitter

Available LVPECL, CMOS, LVDS,

and CML outputs

1.8, 2.5, or 3.3 V supply

Pin- and register-compatible with

Si570/571



Programmable with 28 parts per

trillion frequency resolution

Integrated crystal provides stability

and low phase noise

Frequency changes up to

±3500 ppm are glitchless

–40 to 85 °C operation

Industry-standard 5x7 mm package

Si5602

Applications



Ordering Information:



SONET / SDH / xDSL

Ethernet / Fibre Channel

3G SDI / HD SDI

Multi-rate PLLs

Multi-rate reference clocks

Frequency margining

Digital PLLs

CPU / FPGA FIFO control

Adaptive synchronization

Agile RF local oscillators

See page 21.

Pin Assignments:

See page 20.

(Top View)

SDA

SCL

Description

The Si598 XO/Si599 VCXO utilizes Silicon Laboratories' advanced DSPLL®

circuitry to provide a low-jitter clock at any frequency. They are user-

programmable to any output frequency from 10 to 810 MHz with 28 parts per

trillion (PPT) resolution. The device is programmed via a 2-pin I

C compatible

serial interface. The wide frequency range and ultra-fine programming resolution

make these devices ideal for applications that require in-circuit dynamic frequency

adjustments or multi-rate operation with non-integer related rates. Using an

integrated crystal, these devices provide stable low jitter frequency synthesis and

replace multiple XOs, clock generators, and DAC controlled VCXOs.

GND

CLK–

CLK+

Functional Block Diagram

Power Supply Filtering

Si598

SDA

Fixed

Frequency

Oscillator

Any Frequency

DSPLL®

10 to 810 MHz

Clock Synthesis

CLK+

CLK–

SCL

(Si599)

CLK–

CLK+

ADC

I2C Interface

GND

SDA

SCL

GND

Si599

Rev. 1.1 6/18

Si598/Si599

Recommended Resources

Double button light switch circuit (11)

Telephone off-hook indicator circuit diagram

Macro YPF5-4 range hood circuit diagram

Light controlled electronic bird circuit

Miniaturized isolation amplifier circuit diagram

Micropower voltage detection integrated chip MAX834/835 with latch output

Source synchronous timing issues: Many ASIC peripherals now use DDR (II) SDRAM (SRAM). Due to the high data transmission rate, data signals are basically source synchronous. Many timing materials believe that there is no length limit ...; eeleader FPGA/CPLD

PIC direct drive TFT true color LCD module data: ...; gxkj001 Microchip MCU

Digitally controlled power supply using DSP for secondary voltage regulation: [[i] This post was last edited by lrz123 on 2011-10-25 10:48[/i]]...; lrz123 DIY/Open Source Hardware

About the digital tube display problem: I have been using FPGA to make a digital clock these days, using six digital tubes for display. I used a 20M crystal oscillator and divided it to get a 1KHZ signal, and used this signal to scan the bi...; gavin_8724 FPGA/CPLD

Power supply noise: I use lithium batteries to power a microcontroller through a switching step-down power supply to collect data from a vibration sensor. However, the noise from the power supply always affects the data ...; stuwang Power technology

Why are the first four bytes of a physical sector of an SD card or USB flash drive sometimes written as RRaA by the system?: I write an identifier to the physical sector of a USB flash drive through a filter driver I wrote. I write it starting from the first digit, for example "asdd12344". But sometimes for some reason, the...; hyhjjg Embedded System

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components