EEWORLDEEWORLDEEWORLD

Part Number

Search

813001AGI

Description
PLL/Frequency Synthesis Circuit, PDSO24
CategoryAnalog mixed-signal IC    The signal circuit   
File Size264KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

813001AGI Overview

PLL/Frequency Synthesis Circuit, PDSO24

813001AGI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
JESD-30 codeR-PDSO-G24
JESD-609 codee0
Humidity sensitivity level1
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply2.5/3.3 V
Certification statusNot Qualified
Maximum supply current (Isup)130 mA
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Base Number Matches1
Dual VCXO w/3.3V, 2.5V LVPECL
FemtoClock™ PLL
G
ENERAL
D
ESCRIPTION
The 813001I is a dual VCXO + FemtoClock™ Multiplier de-
signed for use in Discrete PLL loops. Two selectable external
VCXO crystals allow the device to be used in multi-rate appli-
cations, where a given line card can be switched, for example,
between 1Gb Ethernet (125MHz system reference clock) and
1Gb Fibre Channel (106.25MHz system reference clock) modes.
Of course, a multitude of other applications are also possible
such as switching between 74.25MHz and 74.175824MHz for
HDTV, switching between SONET, FEC and non FEC rates, etc.
The 813001I is a two stage device – a VCXO followed
by a FemtoClock PLL. The FemtoClock PLL can multiply
the crystal frequency of the VCXO to provide an output
frequency range of 40.83MHz to 640MHz, with a random rms
phase jitter of less than 1ps (12kHz – 20MHz). This phase jitter
performance meets the requirements of 1Gb/10Gb Ethernet,
1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to
OC48. The FemtoClock PLL can also be bypassed if frequen-
cy multiplication is not required. For testing/debug purposes,
de-assertion of the output enable pin will place both Q and nQ
in a high impedance state.
813001I
DATASHEET
F
EATURES
• One 3.3V or 2.5V LVPECL output pair
• Two selectable crystal oscillator interfaces for the VCXO,
one differential clock or one LVCMOS/LVTTL clock inputs
• CLK1/nCLK1 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Crystal operating frequency range: 14MHz - 24MHz
• VCO range: 490MHz - 640MHz
• Output frequency range: 40.83MHz - 640MHz
• VCXO pull range: ±100ppm (typical)
• Supports the following applications (among others):
SONET, Ethernet, Fibre Channel, HDTV, MPEG
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.84 (typical)
• Supply voltage modes:
V
CC
/V
CCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in RoHS/Lead-Free compliant package
B
LOCK
D
IAGRAM
VCO_SEL
Pullup
CLK_SEL0
Pulldown
CLK_SEL1
Pullup
CLK0
Pulldown
CLK1
Pulldown
nCLK1
Pullup
XTAL_IN0
00
01
PD
10
(default)
0
Output Divider N
N2:N0
000 ÷1
001 ÷2
010 ÷3
011 ÷4
(default)
100 ÷5
101 ÷6
110 ÷8
111 ÷12
VCO
490-640MHz
1
XTAL_OUT0
XTAL_IN1
Q
nQ
VCXO
11
XTAL_OUT1
VC
M2
Pullup
M1
Pulldown
Pulldown
M0
Pulldown
N2
Pullup
N1
Pullup
N0
Pullup
OE
Feedback Divider M
M2:M0
000 ÷16
001 ÷20
010 ÷22
011 ÷24
100 ÷25
(default)
101 ÷32
110 ÷40
111 MR
P
IN
A
SSIGNMENT
VCO_SEL
N0
N1
N2
V
CCO
Q
nQ
V
EE
V
CCA
V
CC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK_SEL1
CLK_SEL0
OE
M2
M1
M0
CLK1
nCLK1
CLK0
VC
XTAL_IN0
XTAL_OUT0
813001I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
1
©2015 Integrated Device Technology, Inc.
813001I REVISION A 3/17/15

813001AGI Related Products

813001AGI 813001AGIT
Description PLL/Frequency Synthesis Circuit, PDSO24 PLL/Frequency Synthesis Circuit, PDSO24
Is it Rohs certified? incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Reach Compliance Code not_compliant not_compliant
JESD-30 code R-PDSO-G24 R-PDSO-G24
JESD-609 code e0 e0
Humidity sensitivity level 1 1
Number of terminals 24 24
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP
Encapsulate equivalent code TSSOP24,.25 TSSOP24,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply 2.5/3.3 V 2.5/3.3 V
Certification status Not Qualified Not Qualified
Maximum supply current (Isup) 130 mA 130 mA
surface mount YES YES
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15)
Terminal form GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm
Terminal location DUAL DUAL
Base Number Matches 1 1
Is there a big difference between Quartus II and ISE?
The clock frequency of timing simulation on Quartus II can be very high, but why is the clock frequency much lower when running the same code on ISE?...
摇动所有的经筒 FPGA/CPLD
Remove an energy-saving lamp
[font=微软雅黑][size=3]A colleague used it as a fill light, but it suddenly stopped working. I took it apart to have a look out of curiosity.[/size][/font] [font=微软雅黑][size=3]What have you taken apart rec...
eric_wang Making friends through disassembly
51AVR MCU Learning Board
51AVR MCU learning board EE21 can do the following experiments: 1. LED running light experiment 2. LED gradual light on and off experiment 3. 8-digit digital tube static display Roman]4[/font][font=宋体...
flzxh200 51mcu
Free trial: ST dual-core wireless MCU STM32WB55 development board
[font=微软雅黑][size=4]STM32WBx5 is the latest dual-core wireless MCU launched by ST in February 2019. It is equipped with Bluetooth 5, OpenThread and ZigBee3.0 connection technologies, and has ultra-low ...
okhxyyo RF/Wirelessly
Power chip
SV625_SOP8 Simplified 2A charge and discharge management mobile power dedicated chip[color=#000][size=0px][color=#8c8c8c][size=14px]2016-03-10[/size][/color] [color=#8c8c8c][size=14px]Tony Le[/size][/...
雨后的梧桐 Analogue and Mixed Signal
High Frequency Power Electronics
http://www.cndzz.com/user/show/1344.htm...
fighting Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 844  2397  952  1898  1523  17  49  20  39  31 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号