DP3S1MX8MY5-80C datasheet, PDF

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DP3S1MX8MY5-80C: DescriptionSRAM Module, 1MX8, 80ns, CMOS, LPSTACK-40; Categorystorage storage; File Size258KB，2 Pages; ManufacturerB&B Electronics Manufacturing Company

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DP3S1MX8MY5-80C Overview

SRAM Module, 1MX8, 80ns, CMOS, LPSTACK-40

DP3S1MX8MY5-80C Parametric

Parameter Name	Attribute value
Maker	B&B Electronics Manufacturing Company
Parts packaging code	MODULE
package instruction	,
Contacts	40
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	80 ns
JESD-30 code	R-XTMA-N40
memory density	8388608 bit
Memory IC Type	SRAM MODULE
memory width	8
Number of functions	1
Number of terminals	40
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX8
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal location	TRIPLE
Base Number Matches	1

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8 Megabit 3.3 Volt CMOS SRAM

16 Megabit 3.3 Volt CMOS SRAM

PRELIMINARY

DESCRIPTION:

The

LP-Stack™

series is a family of interchangeable memory

modules. The 4 Megabit SRAM is a member of this family

which utilizes the new and innovative space saving TSOP

technology. The modules are constructed with 512K x 8,

3.3 Volt SRAM’s.

The 4 Megabit based

LP-Stack™

modules have been designed

to fit in the same footprint as the 512K x 8 SRAM TSOP

monolithic. This allows the memory board designer to

upgrade the memory in their products without redesigning the

memory board, thus saving time and money.

FEATURES:

•

Configurations Available:

8 Megabit:

1 Meg x 8

16 Megabit:

2 Meg x 8

•

Access Times: 70, 85, 100ns (max.)

•

Fully Static Operation - No Clock or Refresh Required

•

Equal Access and Cycle Times

•

3.3 Volt Supply

•

TTL Compatible Inputs and Outputs

•

Package: 40 Pin Leadless LP-Stacks™

DP3S1MX8MY5 (2-High LP-Stack)

DP3S2MX8MY5 (4 High LP-Stack)

PIN-OUT DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

PIN NAMES

A0 - A18

DQ0 - DQ7

CS0 - CS3

WE

OE

V

DD

V

SS

N.C.

Address

Data In / Data Out

Chip Selects

Write Enable

Output Enable

Power Supply (+3.3V)

Ground

No Connect

30A230-10

REV. B

This document contains information on a product presently under

development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the

right to change products or specifications herein without prior notice.

1

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