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IDT74FCT245AQB

Description
FCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20
Categorysemiconductor    logic   
File Size73KB,6 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT74FCT245AQB Overview

FCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20

IDT74FCT245AQB Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage5.25 V
Minimum supply/operating voltage4.75 V
Rated supply voltage5 V
Number of ports2
Processing package descriptionSOIC-20
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
seriesFCT
Output characteristics3-ST
Logic IC typetransceiver
Number of digits8
Output polarityTRUE
propagation delay TPD4.6 ns
3.3V CMOS OCTAL
BIDIRECTIONAL
TRANSCEIVERS
Integrated Device Technology, Inc.
IDT54/74FCT3245/A
FEATURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• 25 mil Center SSOP and QSOP Packages
• Extended commercial range of -40°C to +85°C
• V
CC
= 3.3V
±0.3V,
Normal Range or
V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The FCT3245/A octal transceivers are built using ad-
vanced dual metal CMOS technology. These high-speed,
low-power transceivers are ideal for synchronous communi-
cation between two busses (A and B). The direction control
pin (DIR) controls the direction of data flow. The output enable
pin (
OE
) overrides the direction control and disables both
ports. All inputs are designed with hysteresis for improved
noise margin.
The FCT3245/A have series current limiting resistors.
These offer low ground bounce, minimal undershoot, and
controlled output fall times-reducing the need for external
series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIR
1
2
3
4
5
6
7
8
9
10
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
20
19
18
17
16
15
14
13
12
11
Vcc
OE
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
DIR
OE
A
1
B
1
A
2
B
2
A
3
B
3
A
4
B
4
A
5
B
5
A
6
B
6
A
7
B
7
A
8
B
8
2650 drw 01
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
GND
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
DIR
V
CC
A
2
A
1
OE
INDEX
2650 drw 02
3 2
A
3
A
4
A
5
A
6
A
7
4
5
6
7
8
L20-2
1
20 19
18
17
16
15
14
B
1
B
2
B
3
B
4
B
5
9 10 11 12 13
GND
A
8
B
8
B
7
B
6
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC
TOP VIEW
2650 drw 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
FEBRUARY 1996
DSC-2650/5
8.12
1

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