v6.0
40MX and 42MX FPGA Families
Fe a t ur es
High C apaci t y
•
•
•
•
•
•
•
•
•
•
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
• Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
• QML Certification
• Ceramic Devices Available to DSCC SMD
E ase of Int egr at io n
High P er f or m ance
• Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os),
with PCI-Compliant I/Os
• Up to 100% Resource Utilization and 100% Pin Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• Low Power Consumption
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
HiR el Feat ur es
• Commercial, Industrial, Automotive, and Military
Temperature Plastic Packages
Pr od uc t P r o f i l e
Device
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
Clock-to-Out
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
User I/O (maximum)
PCI
Boundary Scan Test (BST)
Packages (by pin count)
)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
A40MX02
3,000
–
–
295
–
9.5 ns
–
–
147
1
57
–
–
44, 68
100
80
–
–
–
A40MX04
6,000
–
–
547
–
9.5 ns
–
–
273
1
69
–
–
44, 68, 84
100
80
–
–
–
A42MX09
14,000
–
348
336
–
5.6 ns
–
348
516
2
104
–
–
84
100, 160
100
176
–
–
A42MX16
24,000
–
624
608
–
6.1 ns
–
624
928
2
140
–
–
84
100, 160, 208
100
176
–
–
A42MX24
36,000
–
954
912
24
6.1 ns
–
954
1,410
2
176
Yes
Yes
84
160, 208
–
176
–
–
A42MX36
54,000
2,560
1,230
1,184
24
6.3 ns
10
1,230
1,822
6
202
Yes
Yes
–
208, 240
–
–
208, 256
272
J an u a r y 2 0 0 4
1
© 2004 Actel Corporation
40MX and 42MX FPGA Families
O r d e r i n g I nf o r m a t i o n
A42MX16
PQ
100
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
A = Automotive (–40 to +125°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
BG = Plastic Ball Grid Array
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
=
=
=
=
=
=
3,000 System Gates
6,000 System Gates
14,000 System Gates
24,000 System Gates
36,000 System Gates
54,000 System Gates
Pl a s t i c D e vi c e Re so u r ce s
User I/Os
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
PLCC
44-Pin
34
34
–
–
–
–
PLCC
68-Pin
57
57
–
–
–
–
PLCC
84-Pin
–
69
72
72
72
–
PQFP
PQFP
PQFP
PQFP
100-Pin 160-Pin 208-Pin 240-Pin
57
69
83
83
–
–
–
–
101
125
125
–
–
–
–
140
176
176
–
–
–
–
–
202
VQFP
80-Pin
57
69
–
–
–
–
VQFP
TQFP
PBGA
100-Pin 176-Pin 272-Pin
–
–
83
83
–
–
–
–
104
140
150
–
–
–
–
–
–
202
Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array
C er a m i c De v i ce R es ou r c es
User I/Os
Device
A42MX36
CQFP
208-Pin
176
CQFP
256-Pin
202
Package Definitions
CQFP = Ceramic Quad Flat Pack
2
v6.0
40MX and 42MX FPGA Families
G en er al D e sc r i p t i on
M X A r ch i t e c t ur al O v erv i ew
Actel’s 40MX and 42MX families offer a cost-effective design
solution at 5V. The MX devices are single-chip solutions and
provide high performance while shortening the system
design and development cycle. MX devices can integrate and
consolidate logic implemented in multiple PALs, CPLDs,
and FPGAs. Example applications include high-speed
controllers and address decoding, peripheral bus interfaces,
DSP, and co-processor functions.
The MX device architecture is based on Actel’s patented
antifuse technology implemented in a 0.45µm triple-metal
CMOS process. With capacities ranging from 3,000 to 54,000
system gates, the MX devices provide performance up to
250 MHz, are live on power-up and have one-fifth the
standby power consumption of comparable FPGAs. Actel’s
MX FPGAs provide up to 202 user I/Os and are available in a
wide variety of packages and speed grades.
Actel’s A42MX24 and A42MX36 devices also feature
MultiPlex I/Os, which support mixed-voltage systems,
enable programmable PCI, deliver high-performance
operation at both 5.0V and 3.3V, and provide a low-power
mode. The devices are fully compliant with the PCI Local
Bus Specification (version 2.1). They deliver 200 MHz
on-chip operation and 6.1 ns clock-to-output performance.
The 42MX24 and 42MX36 devices include system-level
features such as IEEE Standard 1149.1 (JTAG) Boundary
Scan Testing and fast wide-decode modules. In addition, the
A42MX36 device offers dual-port SRAM for implementing
fast FIFOs, LIFOs, and temporary data storage. The storage
elements can efficiently address applications requiring wide
datapath manipulation and can perform transformation
functions such as those required for telecommunications,
networking, and DSP.
All MX devices are fully tested over automotive and military
temperature ranges. In addition, the largest member of the
family, the A42MX36, is available in both CQ208 and CQ256
ceramic packages screened to MIL-STD-883 levels. For easy
prototyping and conversion from plastic to ceramic, the
CQ208 and PQ208 devices are pin-compatible.
The MX devices are composed of fine-grained building
blocks that enable fast, efficient logic designs. All devices
within these families are composed of logic modules, I/O
modules, routing resources and clock networks, which are
the building blocks for fast logic designs. In addition, the
A42MX36 device contains embedded dual-port SRAM
modules, which are optimized for high-speed datapath
functions such as FIFOs, LIFOs and scratchpad memory.
A42MX24 and A42MX36 also contain wide-decode modules.
Lo gic Mod ule s
The 40MX logic module is an eight-input, one-output logic
circuit designed to implement a wide range of logic
functions with efficient use of interconnect routing
resources (Figure
1).
The logic module can implement the four basic logic
functions (NAND, AND, OR and NOR) in gates of two, three,
or four inputs. The logic module can also implement a
variety of D-latches, exclusivity functions, AND-ORs and
OR-ANDs. No dedicated hard-wired latches or flip-flops are
required in the array; latches and flip-flops can be
constructed from logic modules whenever required in the
application.
Figure 1 •
40MX Logic Module
4
v6.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
The 42MX devices contain three types of logic modules:
combinatorial (C-modules), sequential (S-modules) and
decode (D-modules).
Figure 2
illustrates the combinatorial
logic module. The S-module, shown in
Figure 3,
implements
the same combinatorial logic function as the C-module
while adding a sequential element. The sequential element
can be configured as either a D-flip-flop or a transparent
latch. The S-module register can be bypassed so that it
implements purely combinatorial logic.
A0
B0
S0
D00
D01
D10
D11
S1
A1
B1
Y
Figure 2 •
42MX C-Module Implementation
D00
D01
D10
D11
S1
Y
S0
CLR
D
Q
OUT
D00
D01
D10
D11
S1
Y
S0
D
GATE
Q
OUT
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Up to 7-Input Function Plus Latch
D00
D0
Y
D1
S
D
GATE
CLR
Q
OUT
D01
D10
D11
S1
S0
Y
OUT
Up to 4-Input Function Plus Latch with Clear
Up to 8-Input Function (Same as C-Module)
Figure 3 •
42MX S-Module Implementation
v6.0
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
