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IDT74FCT377TSO

Description
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
File Size73KB,7 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

IDT74FCT377TSO Overview

FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
Integrated Device Technology, Inc.
IDT54/74FCT377T/AT/CT/DT
FEATURES:
Std., A, C and D speed grades
Low input and output leakage
≤1µA
(max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Power off disable outputs permit “live insertion”
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (
CE
) is LOW. The register is fully
edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop’s O output. The
CE
input must be
stable only one set-up time prior to the LOW-to-HIGH transi-
tion for predictable operation.
FUNCTIONAL BLOCK DIAGRAM
D
0
CE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D Q
CP
CP
O
0
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
D Q
CP
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2630 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
APRIL 1995
DSC-4200/3
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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