8 Megabit High Speed CMOS SRAM
DPS1MX8MKN3-A
DESCRIPTION:
The DPS1MX8MKN3-A High Speed SRAM
‘’STACK’’ devices are a revolutionary new memory
subsystem using Dense-Pac Microsystems’ ceramic
Stackable Leadless Chip Carriers (SLCC) mounted
on a co-fired ceramic substrate having side-brazed
leads. The device packs 8-Megabits of low-power
CMOS static RAM in a 600-mil-wide, 32-pin
dual-in-line package.
The DPS1MX8MKN3-A STACK devices contain
two 512K x 8 SRAM die, each packaged in a
hermetically sealed SLCC, making the devices
suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Stack’’ family of devices offer
a higher board density of memory than available
with conventional through-hole, surface mount or
hybrid techniques.
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
•
Organizations Available:
1Meg x 8
•
Access Times:
20*, 25, 30, 35, 45ns
•
Fully Static Operation
•
•
•
•
•
- No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage:
2.0V min.
Package Available:
32 Pin DIP
PIN-OUT DIAGRAM
*
Commercial and Industrial Grade only.
PIN NAMES
A0 - A18
I/O0 - I/O7
CE0, CE1
WE
V
DD
VSS
Address
Data Input / Output
Low Chip Enables
Write Enable
Power (+5.0V)
Ground
30A129-92
REV. A
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS1MX8MKN3-A
TRUTH TABLE
Mode
Not Selected
Read
Write
H = HIGH
CE
H
L
L
WE
X
H
L
I/O Pin
HIGH-Z
D
OUT
D
IN
Supply
Current
Standby
Active
Active
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
3
Symbol
Characteristic
V
DD
Supply Voltage
V
IH
Input HIGH Voltage
V
IL
Input LOW Voltage
M/B
Operating
T
A
I
Temperature
C
Min.
4.5
2.2
-0.5
2
-55
-40
-0
Max. Unit
5.5
V
V
DD
+0.3 V
0.8
V
+25 +125
ºC
+25
+85
+25
+70
Typ.
5.0
L = LOW
X = Don’t Care
ABSOLUTE MAXIMUM RATING
3
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Max.
Unit
Storage Temperature
-65 to +150
ºC
Temperature Under Bias
-55 to +125
ºC
1
Supply Voltage
-0.5 to +7.0
V
Input/Output Voltage
1
-0.5 to V
DD
+0.5 V
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output Timing Reference Levels
0V to 3.0V
5ns*
1.5V
CAPACITANCE
4
:
T
A
= +25ºC, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Data Input/Output
Max.
18
12
18
22
Unit Condition
pF
V
IN2
= 0V
OUTPUT LOAD
Load
1
2
C
L
100pF
5pF
Parametric Measured
except t
LZ
, t
HZ
and t
WHZ
t
LZ
, t
HZ
and t
WHZ
+5V
480Ω
* Including Probe and Jig Capacitance.
Figure 1.
Output Load
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4mA 2.4
V
I
OL
=8mA
0.4
V
D
OUT
C
L
*
255Ω
DC OPERATING CHARACTERISTICS:
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current (3.0V)
Data Retention
Supply Current (2.0V)
Output LOW Voltage
Output HIGH Voltage
Test Condition
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD ,
CE = V
IH
or WE = V
IL
Cycle = min., Duty = 100%,
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3V, CE
≥
V
DR
-0.2V
V
DR
= 2V, CE
≥
V
DR
-0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
Over Operating Ranges
C
I
M/B
Typ.
Unit
(†)
Min. Max. Min. Max. Min. Max.
-
-
145
2
40
300
200
-
-
2.4
-10
-20
+10
+20
230
20
120
1000
600
0.4
2.4
-10
-20
+10
+20
240
20
120
2000
1600
0.4
2.4
-10
-20
+10
+20
240
30
120
4000
360
0.4
µA
µA
mA
mA
mA
µA
µA
V
V
† Typical measurement made at +25°C, Cycle = min., V
DD
= 5.0V.
2
30A129-92
REV. A
Dense-Pac Microsystems, Inc.
DPS1MX8MKN3-A
Data Retention AC Characteristics
8
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data Retention
Chip Disable to Data
Retention Time
Operating Recovery Time
Test Condition
CE
≥
V
DR
-0.2V
See Data Retention Waveform
See Data Retention Waveform
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
No. Symbol
1
2
3
4
5
6
t
RC
t
AA
t
CO
t
CLZ
t
CHZ
t
OH
Parameter
Read Cycle Time
Address Cycle Time
Chip Enable Output Valid
Chip Enable to Output in LOW-Z
4, 6
Chip Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns*
20
20
20
3
8
4
5
3
10
5
25ns
25
25
25
3
15
30ns
30
30
30
Over Operating Ranges
35ns
45ns
35
35
35
3
20
5
5
3
25
45
45
45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
AC OPERATING CONDITION AND CHARACTERISTIC READ CYCLE:
No. Symbol
7
8
9
10
11
12
13
14
15
16
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Setup Time **
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
4, 5
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
20ns*
20
13
13
0
13
0
0
9
0
3
25ns
25
15
15
0
15
0
0
10
0
3
30
20
20
0
20
0
0
12
0
3
Over Operating Ranges
6, 7
30ns
35ns
45ns
35
25
25
0
25
0
0
15
0
3
45
35
35
0
35
0
0
20
0
3
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
12
15
20
* Available in Commercial and Industrial Grade Only.
** Valid for both Read and Write Cycles.
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
30A129-92
REV. A
3
DPS1MX8MKN3-A
Dense-Pac Microsystems, Inc.
READ CYCLE
ADDRESS
CE
DATA I/O
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
4
30A129-92
REV. A
Dense-Pac Microsystems, Inc.
DPS1MX8MKN3-A
WRITE CYCLE 2:
WE Controlled.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
1.
2.
3.
NOTE:
All voltages are with respect to V
SS
.
-2.0V min. for pulse width less than 20ns (V
IL
min. = -0.5V
at DC level).
Stresses greater than those under
ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4.
5.
6.
7.
8.
This parameter is guaranteed and not 100% tested.
Transition is measured at the point of
±500mV
from steady
state voltage.
When CE is LOW and WE is HIGH, I/O pins are in the
output state, and input signals of opposite phase to the
outputs must not be applied.
The outputs are in a high impedance state when WE is
LOW.
CE and WE can initiate and terminate WRITE Cycle.
WAVEFORM KEY
Data Valid
HIGH to LOW
Transition from
LOW to HIGH
Transition from
or Don’t Care
Data Undefined
30A129-92
REV. A
5
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