The UT54ALVC2525 is a low-voltage, minimum skew, one-
to-eight clock driver. The UT54ALVC2525 distributes a single
clock to eight, high-drive, outputs with low skew across all
outputs during both the t
PLH
and t
PHL
transitions making it
ideal for signal generation and clock distribution. The output
pins act as a single entity and will follow the state of the CLK
pin.
O
0
O
2
NC
GND
V
DD
O
4
O
6
1
2
3
4
5
6
7
UT54ALVC2525
14
13
12
11
10
9
8
O
1
O
3
CLK
V
DD
GND
O
5
O
7
0
0
Figure 2. 14-Lead Ceramic Flatpack Pinouts
CLK
0
7
Figure 1: UT54ALVC2525 Block Diagram
1
PIN DESCRIPTION
Flatpack
Pin No.
12
3
1, 2, 6, 7, 8, 9,
13, 14
5, 11
4, 10
Name
CLK
N/C
O
n
V
DD
V
SS
I/O
I
--
O
PWR
PWR
Type
LVTTL
--
LVTTL
Power
Power
Description
Primary reference clock input. This pin must be driven by an LVTTL or
LVCMOS clock source.
No connect.
Eight output clocks.
Power supply for internal circuitry and output buffers.
Ground
OPERATIONAL ENVIRONMENT
The UT54ALVC2525 incorporates special design, layout, and process features which allows operation in a limited HiRel environment.
Parameter
Total Ionizing Dose (TID)
Single Event Latchup (SEL)
1, 2
Onset Single Event Upset (SEU) LET (@2.0V)
3, 5
Onset Single Event Upset (SEU) LET (@3.0V)
4, 5
Neutron Fluence
Dose Rate Upset
Dose Rate Survivability
Limit
>1E6
>111
52
66
1.0E14
TBD
TBD
Units
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
rads(Si)/sec
rads(Si)/sec
Notes:
1. The UT54ALVC2525 is latchup immune to particle LETs >111 MeV-cm
2
/mg.
2. SEL temperature and voltage conditions of T
C
= +125
o
C, V
DD
= 3.6V.
3. SEU temperature and voltage conditions of T
C
= +25
o
C, V
DD
= 2.0V. Tested at 200MHz.
4. SEU temperature and voltage conditions of T
C
= +25
o
C, V
DD
= 3.0V. Tested at 200MHz.
5. For the UT54ALVC2525 SET performance at select operating frequency data ranges, please contact the factory.
2
ABSOLUTE MAXIMUM RATINGS:
1
(Referenced to V
SS
)
Symbol
V
DD
V
IN
V
OUT
I
I
P
D
T
STG
T
J
Θ
JC
ESD
HBM
Description
Core Power Supply Voltage
Voltage Any Clock Input
Voltage Any Clock Output
DC Input Current
Maximum Power Dissipation
Storage Temperature
Maximum Junction Temperature
2
Thermal Resistance, Junction to Case
ESD Protection (Human Body Model) - Class II
Limits
-0.3 to 4.0
-0.3 to V
DD
+ 0.3
-0.3 to V
DD
+ 0.3
+10
1
-65 to +150
+150
20
>3000
Units
V
V
V
mA
W
°C
°C
°C/W
V
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
RECOMMENDED OPERATING CONDITIONS:
Symbol
V
DD
V
IN
V
OUT
T
C
Description
Core Operating Voltage
Voltage Clock Input
Voltage Any Clock Output
Case Operating Temperature
Limits
2.0 to 3.6
0 to V
DD
0 to V
DD
-55 to +125
Units
V
V
V
°C
3
DC ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(V
DD
= 2.0V to 3.6V; T
C
= -55°C to +125°C)
Symbol
Description
Conditions
V
DD
2.0V
2.75V
3.0V
3.6V
2.0V
2.75V
3.0V
3.6V
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 12mA
I
OH
= -12mA
I
OH
= -12mA
I
OH
= -12mA
I
OH
= -12mA
V
OUT
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
2.0V
2.75V
3.0V
3.6V
2.0V
2.75V
3.0V
3.6V
2.0V
3.6V
3.6V
1.5
2.2
2.4
3.0
-200
-300
-1
200
300
1
1.0
1.0
Min.
1.25
1.5
1.75
2.0
Max.
Units
V
IH1
High level input voltage
V
V
IL1
Low level input voltage
0.7
0.8
0.8
0.8
0.45
0.4
0.4
0.4
V
V
OL
Low level output voltage
V
V
OH
High level output voltage
V
I
OS2
I
IL
I
DDQ
Short-circuit output current
Input leakage current
Quiescent Supply Current
mA
μΑ
mA
V
IN
= V
DD
or V
SS
2.0V
3.6V
2.0V
2.75V
3.0V
3.6V
0V
0V
P
TOTAL3
Total power dissipation
C
L
= 20pF
1.2
2.7
3.5
5.2
mW/MHz
C
IN4
C
OUT4
Input capacitance
Output capacitance
f = 1MHz
f = 1MHz
15
15
pF
pF
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. Functional tests are conducted in accordance with MIL-STD-883 with the following test conditions: V
IH
=V
IH
(min) +20%, -0% V
IL
=V
IL
(max)+0%, -50%, as
specified herein for the LVTTL and LVCMOS inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to
V
IH
(min), V
IL
(max).
2. Supplied as a design limit. Neither guaranteed nor tested.
3. When measuring the dynamic supply current, all outputs are loaded in accordance with the equivalent test load defined in figure 3.
4. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and the VSS at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
4
AC ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(V
DD
= 2.0V to 3.6V; T
C
= -55°C to +125°C)
Symbol
t
R
, t
F3
Description
Input rise/fall time
Propagation delay:
CLK to On,
high-to-low transition
Propagation delay:
CLK to On,
low-to-high transition
Maximum skew:
common edge,
output-to-output,
high-to-low transition
Maximum skew:
common edge,
output-to-output,
low-to-high transition
Output rise/fall time
Condition
V
IH
(min) - V
IL
(max)
Measured as transition time between
V
IN
= V
DD
÷2
to V
OUT
= V
DD
÷2
V
DD
3.6V
2.0V
2.75V
3.0V
3.6V
2.0V
2.75V
3.0V
3.6V
2.0V
3.6V
Min.
Max.
20
Unit
ns/V
t
PHL1,2
3.5
3.0
2.75
2.25
3.25
2.75
2.5
2.0
7.5
5.5
5.25
4.75
7.25
5.25
5.0
4.5
0.15
0.25
ns
t
PLH1,2
Measured as transition time between
V
IN
= V
DD
÷2
to V
OUT
= V
DD
÷2
ns
t
OSHL2,4,5
Measured as V
On
= V
DD
÷2
to V
Om
= V
DD
÷2
where
n,m
= 0 to 7;
n
not equal to
m
@ f
CLK
=
200MHz
ns
t
OSLH
2,4,5
Measured as V
On
= V
DD
÷2
to V
Om
= V
DD
÷2
where
n,m
= 0 to 7;
n
not equal to
m
@ f
CLK
=
200MHz
Measured as transition time between
20% * V
OL
and 80% * V
OH
@ f
CLK
= 100MHz
Skew between the same output of any two devices
under identical settings and conditions
(V
DD
, temp, air flow, frequency, etc).
Measured as transition time between
V
IN
= V
DD
÷2
to V
OUT
= V
DD
÷2
2.0V
3.6V
0.15
0.25
ns
t
ORISE &3
t
OFALL
t
PART4,5
2.0V
3.6V
2.0V
3.6V
2.0V
2.75V
3.0V
3.6V
2.4
2.0
0.1
0.15
0.43
0.3
0.26
0.21
ns
Part-part skew
Propagation delay balance:
difference between same output,
low-to-high and
high-to-low transitions
ns
t
PBAL1,4
ns
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. Test load = 40pF, terminated to V
DD
÷
2. All outputs are equally loaded. Reference Figure 3 for clock output loading.
2. Reference Figure 4 for AC timing diagram.
3. Supplied only as a design guideline, neither tested nor guaranteed.
4. Guaranteed by characterization, but not tested.
5. Test load = 40pF, terminated to V
DD
÷2.
All outputs are equally loaded. Reference Figure 5 for clock output loading.
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