ICS557-03
PCI-E
XPRESS
C
LOCK
S
OURCE
Description
The ICS557-03 is a spread spectrum clock generator
supporting PCI-Express and Ethernet requirements.
The device is used for PC or embedded systems to
substantially reduce electromagnetic interference
(EMI). The device provides two differential (HCSL)
spread spectrum outputs. This device is pin configured
to select spread and clock selection. Using ICS’
patented Phase-Locked Loop (PLL) techniques, the
device takes a 25 MHz crystal input and produces two
pairs of differential outputs (HCSL) at 25 MHz, 100
MHz, 125 MHz and 200 MHz clock frequencies. It also
provides spread selection of ±0.25%, -0.5%, -0.75%,
and no spread.
Features
•
•
•
•
•
•
•
•
•
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Supports LVDS Output Levels
Operating voltage of 3.3 V
Input frequency of 25 MHz
Outputs (HCSL, 0.7 V Current mode differential pair)
Jitter 100 ps (peak-to-peak)
Spread of ±0.25%, -0.5%, -0.75%, and no spread.
Industrial and commercial temperature ranges
Block Diagram
VDD
2
SS1:SS0
S1:S0
2
CLK0
Control
Logic
Phase Lock Loop
CLK1
CLK1
CLK0
2
X1/ICLK
25 MHz
crystal or clock X2
Optional tuning crystal
capacitors
Clock
Buffer/
Crystal
Oscillator
2
GND
OE
Rr(IREF)
MDS 557-03 E
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
●
Revision 061005
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
ICS557-03
PCI-E
XPRESS
C
LOCK
S
OURCE
Pin Assignment
S0
S1
SS0
X1/ICLK
X2
OE
GNDXD
SS1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDXD
CLK0
CLK0
GNDODA
VDDODA
CLK1
CLK1
IREF
Output Select Table 1(MHz)
S1
0
0
1
1
S0
0
1
0
1
CLK(1:0), CLK(1:0)
25M
100M
125M
200M
Spread Selection Table 2
SS1
0
0
1
1
SS0
0
1
0
1
Spread %
Center ±0.25
Down -0.5
Down -0.75
No Spread
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
S0
S1
SS0
X1/ICLK
X2
OE
GNDXD
SS1
IREF
CLK1
CLK1
VDDODA
GNDODA
CLK0
CLK0
VDDXD
Pin
Type
Input
Input
Input
Input
Input
Power
Input
Pin Description
Select pin 0. See Table1. Internal pull-up resistor.
Select pin 1. See Table 1. Internal pull-up resistor.
Spread Select pin 0. See Table 2. Internal pull-up resistor.
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Output enable tri-states outputs and device is not shut down. Internal
pull-up resistor.
Connect to ground.
Spread Select pin 1. See Table 2. Internal pull-up resistor.
Output Crystal connection. Leave unconnected for clock input.
Output Precision resistor attached to this pin is connected to the internal current
reference.
Output HCSL compliment clock output.
Output HCSL clock output.
Power
Power
Connect to voltage supply +3.3 V for output driver and analog circuits
Connect to ground.
Output HCSL compliment clock output.
Output HCSL clock output.
Power
Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
MDS 557-03 E
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 061005
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS557-03
PCI-E
XPRESS
C
LOCK
S
OURCE
Applications Information
External Components
A minimum number of external components are
required for proper operation.
Output Structures
IREF
=2.3 mA
6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01
µF
should be connected
between each VDD pin and the ground plane, as close
to the VDD pin as possible. Do not share ground vias
between components. Route power from power source
through the capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300
ppm of error across temperature in order for the
ICS557-03 to meet PCI Express specifications.
R
R
475
Ω
See Output Termination
Sections - Pages 3 ~ 5
Crystal Capacitors
Crystal capacitors are connected from pins X1 to
ground and X2 to ground to optimize the accuracy of
the output frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-03.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50Ω, then R
R
=
475Ω (1%), providing IREF of 2.32 mA. The output
current (I
OH
) is equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-03 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the
PCI-Express Layout Guidelines
section.
The ICS557-03 can also be configured for LVDS
compatible voltage levels. See the
LVDS Compatible
Layout Guidelines
section.
MDS 557-03 E
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 061005
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS557-03
PCI-E
XPRESS
C
LOCK
S
OURCE
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
R
S
R
T
Differential Routing on a Single PCB
L4 length, Route as coupled
microstrip
100 ohm differential trace.
L4 length, Route as coupled
stripline
100 ohm differential trace.
Differential Routing to a PCI Express Connector
L4 length, Route as coupled
microstrip
100 ohm differential trace.
L4 length, Route as coupled
stripline
100 ohm differential trace.
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
inch
ohm
ohm
Unit
inch
inch
Unit
inch
inch
PCI-Express Device Routing
L1
R
S
L1’
R
S
L2
L2’
R
T
L3’
R
T
L3
L4
L4’
ICS557-03
Output
Clock
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL)
Waveform
700 mV
0
t
OR
0.52 V
0.175 V
500 ps
500 ps
t
OF
0.52 V
0.175 V
MDS 557-03 E
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 061005
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS557-03
PCI-E
XPRESS
C
LOCK
S
OURCE
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
R
P
R
Q
R
T
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
ohm
ohm
ohm
LVDS Device Routing
L1
R
Q
L1’
L3
L3’
R
P
R
T
ICS557-03
Clock
Output
L2’
L2
R
T
LVDS
Device
Load
Typical LVDS Waveform
1325 mV
1000 mV
t
OR
500 ps
500 ps
t
OF
1250 mV
1150 mV
1250 mV
1150 mV
MDS 557-03 E
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 061005
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
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