PLDC20RA10
Reprogrammable Asynchronous
CMOS Logic Device
1PLDC20RA10
Features
•
•
•
•
•
•
•
•
•
Advanced-user programmable macrocell
CMOS EPROM technology for reprogrammability
Up to 20 input terms
10 programmable I/O macrocells
Output macrocell programmable as combinatorial or
asynchronous D-type registered output
Product-term control of register clock, reset and set and
output enable
Register preload and power-up reset
Four data product terms per output macrocell
Fast
— Commercial
t
PD
= 15 ns
t
CO
= 15 ns
t
SU
= 7 ns
— I
CC
max = 85 mA (Military)
•
High reliability
— Proven EPROM technology
— >2001V input protection
— 100% programming and functional testing
•
Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
able
Functional Description
The Cypress PLDC20RA10 is a high-performance, sec-
ond-generation programmable logic device employing a flexi-
ble macrocell structure that allows any individual output to be
configured independently as a combinatorial output or as a
fully asynchronous D-type registered output.
The Cypress PLDC20RA10 provides lower-power operation
with superior speed performance than functionally equivalent
bipolar devices through the use of high-performance 0.8-mi-
cron CMOS manufacturing technology.
The PLDC20RA10 is packaged in a 24 pin 300-mil molded
DIP, a 300-mil windowed cerDIP, and a 28-lead square lead-
less chip carrier, providing up to 20 inputs and 10 outputs.
When the windowed device is exposed to UV light, the 20RA10
is erased and can then be reprogrammed.
— Military
t
PD
= 20 ns
t
CO
= 20 ns
t
SU
= 10 ns
• Low power
— I
CC
max - 80 mA (Commercial)
Logic Block Diagram
V
SS
12
I9
11
I8
10
I7
9
I6
8
I5
7
I4
6
I3
5
I2
4
I1
3
I0
2
PL
1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
13
OE
14
I/O
9
15
I/O
8
16
I/O
7
17
I/O
6
18
I/O
5
19
I/O
4
20
I/O
3
21
I/O
2
22
I/O
1
23
I/O
0
RA10–1
24
V
CC
Cypress Semiconductor Corporation
Document #: 38-03012 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 26, 1997
PLDC20RA10
Selection Guide
Generic Part
Number
20RA10-15
20RA10-20
20RA10-25
20RA10-35
t
PD
ns
Com‘l
15
20
Mil
20
25
35
Com’l
7
10
t
SU
ns
Mil
10
15
20
Com’l
15
20
t
CO
ns
Mil
20
25
35
Com’l
80
80
t
CC
ns
Mil
85
85
85
Pin Configurations
LCC
Top View
NC
I1
I0
PL
V
CC
I/O0
I/O1
STD PLCC/HLCC
Top View
PL
V
CC
I/O0
I/O1
I2
I1
I0
JEDEC PLCC/HLCC
Top View
PL
NC
VCC
I/O0
I/O1
I1
I0
[1]
4 3 2 1 282726
I2
I3
I4
I5
I6
I
7
NC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NC
I3
I4
NC
I5
I6
NC
5
6
7
8
9
10
11
4 3 2 1 2827 26
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NC
I2
I3
I4
NC
I5
I6
I7
5
6
7
8
9
10
11
4 3 2 1 2827 26
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
NC
I/O 5
I/O 6
I/O 7
PLDC20RA10
PLDC20RA10
PLDC20RA10
CG7C324
121314 1516 1718
12131415161718
8
9
V
SS
OE
I/O9
I/O8
NC
121314 1516 1718
7
8
9
V
SS
OE
I/O9
I/O8
RA10–2
RA10–3
8
9
V
SS
NC
OE
I/O9
I/O8
Macrocell Architecture
Figure 1
illustrates the architecture of the 20RA10 macrocell.
The cell dedicates three product terms for fully asynchronous
control of the register set, reset, and clock functions, as well
as, one term for control of the output enable function.
The output enable product term output is ANDed with the input
from pin 13 to allow either product term or hardwired external
control of the output or a combination of control from both
sources. If product-term-only control is selected, it is automat-
ically chosen for all outputs since, for this case, the external
output enable pin must be tied LOW. The active polarity of
each output may be programmed independently for each out-
put cell and is subsequently fixed.
Figure 2
illustrates the out-
put enable options available.
When an I/O cell is configured as an output, combinatorial-only
capability may be selected by forcing the set and reset product
term outputs to be HIGH under all input conditions. This is
achieved by programming all input term programming cells for
these two product terms.
Figure 3
illustrates the available out-
put configuration options.
An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-de-
fined logic functions.
Programmable I/O
Because any of the ten I/O pins may be selected as an input,
the device input configuration programmed by the user may
vary from a total of nine programmable plus ten dedicated in-
puts (a total of nineteen inputs) and one output down to a
ten-input, ten-output configuration with all ten programmable
I/O cells configured as outputs. Each input pin available in a
given configuration is available as an input to the four control
Note:
1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
principal difference is in the location of the “no connect” (NC) pins
Document #: 38-03012 Rev. **
I
I
I
I
I
product terms and four uncommitted product terms of each
programmable I/O macrocell that has been configured as an
output.
An I/O cell is programmed as an input by tying the output en-
able pin (pin 13) HIGH or by programming the output enable
product term to provide a LOW, thereby disabling the output
buffer, for all possible input combinations.
When utilizing the I/O macrocell as an output, the input path
functions as a feedback path allowing the output signal to be
fed back as an input to the product term array. When the output
cell is configured as a registered output, this feedback path
may be used to feed back the current output state to the device
inputs to provide current state control of the next output state
as required for state machine implementation.
Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by
inclusion of register preload capability, which allows the state
of each register to be set by loading each register from an
external source prior to exercising the device. Testing of com-
plex state machine designs is simplified by the ability to load
an arbitrary state without cycling through long test vector se-
quences to reach the desired state. Recovery from illegal
states can be verified by loading illegal states and observing
recovery. Preload of a particular register is accomplished by
impressing the desired state on the register output pin and
lowering the signal level on the preload control pin (pin1) to a
logic LOW level. If the specified preload set-up, hold and pulse
width minimums have been observed, the desired state is
loaded into the register. To insure predictable system initializa-
tion, all registers are preset to a logic LOW state upon pow-
er-up, thereby setting the active LOW outputs to a logic HIGH.
I
I
RA10–4
Page 2 of 14
PLDC20RA10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage......................................... –3.0 V to + 7.0 V
Output Current into Outputs (LOW) .............................16 mA
]
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
DC Program Voltage .................................................... 13.0V
Operating Range
Range
Commercial
Military
[2]
Ambient
Temperature
0
°
C to +75
°
C
–55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[3]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
SC
I
CC1
I
CC2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Leakage Current
Output Leakage Current
Output Short Circuit Current
[5]
Standby Power Supply Current
Power Supply Current at
Frequency
[5]
V
CC
= Min.,
V
IN
=V
IH
or V
IL
V
CC
= Min.,
V
IN
= V
IH
or V
IL
Test Conditions
I
OH
= –3.2 mA
I
OH
= –2 mA
I
OL
= 8 mA
2.0
0.8
–10
–40
–30
Com’l
Mil
V
CC
= Max., Outputs Disabled (In High Z
State) Device Operating at f
MAX
Com’l
Mil
+10
+40
–90
75
80
80
85
Com’l
Mil
0.5
V
V
V
µA
µA
mA
mA
mA
mA
mA
Min.
2.4
Max.
Unit
V
Guaranteed Input Logical HIGH Voltage for All Inputs
[4]
Guaranteed Input Logical LOW Voltage for All Inputs
[4]
V
SS
≤
V
IN
≤
V
CC
, V
CC
= Max
V
CC
= Max., V
SS
≤
V
OUT
≤
V
CC
V
CC
= Max., V
OUT
= 0.5V
[6]
V
CC
= Max., V
IN
= GND Outputs Open
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 2.0 V @ f = 1 MHz
V
OUT
= 2.0 V @ f = 1 MHz
Max.
10
10
Unit
pF
pF
Notes:
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
5. Tested initially and after any design or process changes that may affect these parameters.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5 V has been chosen to
avoid test problems caused by tester ground degradation.
Document #: 38-03012 Rev. **
Page 5 of 14
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