Color TFT LCD Driver
MN838898
1. Type
CMOS LSI source driver for color TFT LCD panels
2. Overview
This LSI converts the digital display data from a personal computer, portable
device, or other source into analog signals for driving a color TFT LCD panel.
3. Features
(1) Power saving driver
(2) Built in DA converter accepting 6-bit digital input (for 262,144 colors)
(3) Choice of 360 and 324 drive outputs
(4) Input data bus at pixel level
(5) Choice of output data format: gray scale or binary
(6) Eleven reference voltage inputs for producing 10 segment gamma
adjustment graph.
(7) Set output voltage inflection points at data values 00, 01, 07, 0F, 17, 1F,
27, 2F, 37, 3E, and 3F.
(8) Prechargeless drive circuits
(9) Support for serial cascade connections
(10) Automatic internal clock stop after fixed number of data inputs
(11) Choice of shift register shift direction: right or left
(12) Gray scale data inversion available every clock cycle
(13) Low voltage operation: 2.5 V (typ.) for logic circuits; 3.5 V (typ.)
for analog circuits
(14) Maximum operating clock frequency: 15 MHz
(15) Power save function for cutting off current to outputs, fixing them
at high impedance
Publication date: August 2002
SDF00030AEM
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MN838898
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Descriptions
Pin
Pin Name
I/O
Direction
Table 5.1 Pin Descriptions
Pin Function
Gray scale digital data
input pins
Description
Input pins for gray scale (MODE2 = Low)
digital data, 6 bits each for R, G, and B.
DX5, DY5, and DZ5 represent the MSB;
DX0, DY0, and DZ0, the LSB.
Input pins for binary (MODE2 = High)
digital data, 1 bit each for R, G, and B.
Always drive the unused pins
(DX4 to DX0, DY4 to DY0, and DZ4 to DZ0)
at either High or Low level.
DX0 to 5,
DY0 to 5,
DZ0 to 5
Input
Binary digital data
input pins
(DX5, DY5, and DZ5)
YX1 to 120,
YY1 to 120,
YZ1 to 120
Output
Analog image output pins These signals drive the LCD panel.
These I/O pins are for the internal shift register's start pulses.
The following table indicates data shift direction by start pulses
during face up.
STH R, STHL
I/O
Start pulse I/O pins
RL =H
STHR
STHL
Right shift input
Right shift output
RL=L
Left shift output
Left shift input
RL
FY
LD
INV
MODE1
Input
Input
Input
Input
Input
Shift direction input pin
Shift clock input pin
Data load input pin
Data inversion control
input pin
Number of drive outputs
select pin
This specifies the shift direction: High level for right;
Low level for left.
H: Right shift input (YX,YY,YZ1
→
120)
L: Left shift input
(YX,YY,YZ120
→
1)
This accepts the transfer clock for the shift register
High level input enables transfer, synchronized with rising
edges in the FY signal, of the LCD drive data from the built-
in DA converter.
The data logic when the INV input is at Low level is AVDD for Low
level and AVSS for High level. Driving INV at High level reverses
the data logic.
This specifies the number of LCD panel drive outputs:
High level for 360, Low level for 324, disabling
YX55 to YX66, YY55 to YY66, and YZ55 to YZ66.
(For further details, see Section 6.1 "Functional Description.")
This specifies the data input format: gray scale or binary.
High level: Binary. DX5, DY5, and DZ5 only. The DA
converter is off.
Low level: Gray scale. DX, DY, and DZ5
to DZ0. The DA converter is on.
High level input at a rising edge in the FY signal
cuts off current to outputs, fixing them
at high-impedance.
High level: High-impedance outputs. No current
to operational amplifier
or other components.
Low level: Normal operation
Normally fix this input at High level.
High level: Normal operation
Low level: Test mode
MODE2
Input
Input format select pin
PS
Input
Power save function
select pin
NTEST
VREF
0 to 10
AV
DD
, AV
SS
AV
DD1
, AV
SS1
AV
DD2
, AV
SS2
DV
DD
, DV
SS
Input
Input
Input
Input
Input
Input
Test input pin
(with built-in pull-up
resistance)
Gamma adjustment
potential input pin
Analog power supply
Analog power supply
Analog power supply
Digital power supply
This input is the gamma adjustment potential input pin
for the DA converter.
This is the power supply for the DA converter's analog
circuits.
This is the power supply for the output analog circuits.
This is the power supply for the circuits protecting the output
circuits.
This is the power supply for the digital circuits.
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MN838898
6.2
Relationships Between Data Input and Output Pins
(1) Gray scale data input (MODE2 = Low)
The following summarizes the relationships between data input and output pins for gray scale
data input (MODE2 = Low).
So, binary data input is naturally ignored during gray scale data input.
MODE2 = Low, RL = High
Rn
Bn
Gn
6
6
6
DX0 to 5
DY0 to 5
Source driver shifts right (RL = High)
YX2 YY2 YZ2
YX120YY120 YZ120
324 outputs
DZ0 to 5
YX1 YY1 YZ1
n=1, 2,
½½
,120 (108)
½
R1
R1
B1
B1
G1
G1
R2
R2
B2
B2
G2
G2
(R108) (B108) (G108)
R120 B120 G120
R120 B120 G120
(R108) (B108) (G108)
R1
B1
G1
R2
B2
G2
(R108) (B108) (G108)
R120 B120 G120
MODE2 = Low, RL = Low
R1
R1
B1
B1
G1
G1
R2
R2
B2
B2
G2
G2
324 outputs
(R108) (B108) (G108)
(R108) (B108) (G108)
R120 B120 G120
R120 B120 G120
R1
B1
G1
R2
B2
G2
(R108) (B108) (G108)
R120 B120 G120
Rn
Bn
Gn
6
6
6
YZ120 YY120YX120YZ119YY119YX119
DZ0 to 5
DY0 to 5
DX0 to 5
YZ1 YY1 YX1
Source driver shifts left (RL = Low)
n=1, 2,
½½
,120 (108)
½
(2) Binary input (MODE2 = High)
Binary input uses only the pins DX5, DY5, and DZ5. The relationships between data input
and output pins are otherwise the same.
So, binary data input is naturally ignored during gray scale data input.
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