®
HIGH-PERFORMANCE
CMOS BUS INTERFACE
LATCHES
DESCRIPTION:
IDT54/74FCT841A/B/C
Integrated Device Technology, Inc.
FEATURES:
• Equivalent to AMD’s Am29841-46 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
• IDT54/74FCT841A equivalent to FAST™ speed
• IDT54/74FCT841B 25% faster than FAST
• IDT54/74FCT841C 40% faster than FAST
• Buffered common latch enable, clear and preset inputs
• I
OL
= 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT840 series bus interface latches are
designed to eliminate the extra packages required to buffer
existing latches and provide extra data width for wider address/
data paths or buses carrying parity. The IDT54/74FCT841 is
a buffered, 10-bit wide version of the popular ‘373 function.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in the high-imped-
ance state.
FUNCTIONAL BLOCK DIAGRAM
D
0
PRE
D
N
D P
LE Q
CLR
CLR
D P
LE Q
CLR
LE
OE
Y
0
Y
N
2607 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994
Integrated Device Technology, Inc.
APRIL 1994
DSC-4603/2
7.22
1
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
P24-1
D24-1
E24-1
&
SO24-2
21
20
19
18
17
16
15
14
13
DIP/CERPACK/SOIC
TOP VIEW
2607 drw 02
D
8
D
9
GND
NC
LE
Y
9
Y
8
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
INDEX
D
2
D
3
D
4
NC
D
5
D
6
D
7
D
1
D
0
OE
NC
V
CC
Y
0
Y
1
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18
3
2
1
28 27 26
25
24
23
L28-1
22
21
20
19
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
LCC
TOP VIEW
2607 drw 03
PIN DESCRIPTION
FUNCTION TABLE
(1)
Inter-
Out-
puts
Y
I
Z
Z
Z
Z
L
H
NC
H
L
H
Z
Z
Function
High Z
High Z
High Z
Latched (High Z)
Transparent
Transparent
Latched
Preset
Clear
Preset
Latched (High Z)
Latched (High Z)
2607 tbl 02
CLR
D
I
LE
Name
I/O
I
I
I
Description
When
CLR
is LOW, the outputs are
LOW if
OE
is LOW. When
CLR
is HIGH,
data can be entered into the latch.
The latch data inputs.
The latch enable input. The latches are
transparent when LE is HIGH. Input
data is latched on the HIGH-to-LOW
transition.
The 3-state latch outputs.
The output enable control. When
OE
is
LOW, the outputs are enabled. When
OE
is HIGH, the outputs (Y
I
) are in the
high-impedance (off) state.
Preset line. When
PRE
is LOW, the
outputs are HIGH if
OE
is LOW. Preset
overrides
CLR
.
2607 tbl 01
CLR PRE OE
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
L
H
L
H
H
H
H
L
L
L
L
L
L
H
H
Inputs
LE
X
H
H
L
H
H
L
X
X
X
L
L
D
I
X
L
H
X
L
H
X
X
X
X
X
X
nal
Q
I
X
L
H
NC
L
H
NC
H
L
H
L
H
Y
I
O
I
OE
PRE
I
NOTE:
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,
Z = High Impedance
7.22
2
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
(2)
Terminal Voltage
V
TERM
with Respect to
GND
(3)
Terminal Voltage
V
TERM
with Respect to
GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
P
T
Power Dissipation
I
OUT
DC Output
Current
Commercial
–0.5 to +7.0
Military
Unit
–0.5 to +7.0
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input
Capacitance
Output
Capacitance
(1)
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
2607 tbl 04
–0.5 to V
CC
–0.5 to V
CC
V
°C
°C
°C
W
mA
0 to +70
–55 to +125
–55 to +125
0.5
120
–55 to +125
–65 to +135
–65 to +150
0.5
120
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
2607 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
OH
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32
µ
A
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
I
OH
= –300
µ
A
I
OH
= –15mA MIL.
I
OH
= –24mA COM'L.
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300
µ
A
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 300
µ
A
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
Off State (High Impedance)
Output Current
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
O
= V
CC
V
O
= 2.7V
V
O
= 0.5V
V
O
= GND
Min.
2.0
—
—
—
—
—
—
—
—
—
—
–75
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
10
10
(4)
–10
(4)
–10
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.5
0.5
2607 tbl 05
Unit
V
V
µ
A
µ
A
V
mA
V
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.22
3
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
= GND
LE = V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE
= GND
LE = V
CC
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE
= GND
LE = V
CC
Eight Bits Toggling
Min.
—
—
V
IN
≥
V
HC
V
IN
≤
V
LC
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2.0
0.25
Unit
mA
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
1.7
4.0
mA
—
2.0
5.0
—
3.2
6.5
(5)
—
5.2
14.5
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VC
C
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2607 tbl 06
7.22
4
IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841A
Com'l.
Symbol
Parameter
Propagation Delay
D
I
to Y
I
(LE = HIGH)
Mil.
FCT841B
Com'l.
Mil.
FCT841C
Com'l.
Mil.
Conditions
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Unit
t
PLH
t
PHL
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
1.5
9.0
1.5 10.0 1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0
1.5 12.0 1.5 13.0 1.5
8.0
1.5 10.5 1.5
6.4
1.5
6.8
ns
t
PLH
t
PHL
Propagation Delay
LE to Y
I
1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0 1.5 15.0 1.5 16.0
1.5 12.0 1.5 14.0 1.5
8.0
1.5 10.0 1.5
7.0
9.0
9.0
9.0
6.5
1.5
9.0
ns
ns
t
PLH
t
PHL
t
PHL
t
PLH
t
PZH
t
PZL
Propagation Delay,
PRE
to Y
I
Propagation Delay,
CLR
to Y
I
Output Enable Time
OE
to Y
I
1.5 14.0 1.5 17.0 1.5 10.0 1.5 13.0 1.5
1.5 13.0 1.5 14.0 1.5 10.0 1.5 11.0 1.5
1.5 14.0 1.5 17.0 1.5 10.0 1.5 10.0 1.5
1.5 12.0
1.5 10.0
1.5
1.5
9.0
7.3
ns
C
L
= 50pF
1.5 11.5 1.5 13.0 1.5
8.0
1.5
8.5
1.5
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
t
SU
t
H
t
W
t
W
t
W
t
REM
t
REM
Data to LE Set-up Time
Data to LE Hold Time
LE Pulse Width
(3)
HIGH
R
L
= 500Ω
C
L
= 300pF
(4)
1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0 1.5 12.0 1.5 13.0
R
L
= 500Ω
C
L
= 5pF
(4)
1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 1.5 5.7 1.5 6.0
R
L
= 500Ω
C
L
= 50pF
1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 1.5 6.0 1.5 6.3
R
L
= 500Ω
C
L
= 50pF
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 —
R
L
= 500Ω
2.5
4.0
5.0
4.0
4.0
3.0
—
—
—
—
—
—
3.0
5.0
7.0
5.0
4.0
3.0
—
—
—
—
—
—
2.5
4.0
4.0
4.0
4.0
3.0
—
—
—
—
—
—
2.5
4.0
4.0
4.0
4.0
3.0
—
—
—
—
—
—
2.5
4.0
4.0
4.0
4.0
3.0
—
—
—
—
—
—
2.5
4.0
4.0
4.0
4.0
3.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
PRE
Pulse Width
(3)
LOW
CLR
Pulse Width
(3)
LOW
Recovery Time
PRE
to LE
Recovery Time
CLR
to LE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. These conditions are guaranteed but not tested.
2607 tbl 07
7.22
5
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