IS42VM16200C
Advanced Information
1M
x
16Bits
x
2Banks Low Power Synchronous DRAM
Description
These IS42VM16200C are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits.
These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 1.8V power supply.
•
Auto refresh and self refresh.
•
All pins are compatible with LVCMOS interface.
•
4K refresh cycle / 64ms.
•
Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
•
Programmable CAS Latency : 2,3 clocks.
•
Programmable Driver Strength Control
- Full Strength or 1/2, 1/4 of Full Strength
•
Deep Power Down Mode.
•
All inputs and outputs referenced to the positive edge of the
system clock.
•
Data mask function by DQM.
•
Internal dual banks operation.
•
Burst Read Single Write operation.
•
Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
•
Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Copyright © 2009 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Rev.00A
1
IS42VM16200C
Advanced Information
Table2: Pin Descriptions
Pin
CLK
Pin Name
System Clock
Descriptions
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
Row Address
Column Address
Auto Precharge
: RA0~RA10
: CA0~CA8
: A10
CKE
/CS
BA
Clock Enable
Chip Select
Bank Address
A0~A10
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
/RAS, /CAS, /WE
RAS, CAS and WE define the operation.
Refer function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Multiplexed data input/output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
LDQM,UDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Rev.00A
3
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
