HD121/125
ADP SRAM I
o
5 Volt x8 Asynchronous Dual-Port Static RAM
Memory Configuration
2K x 9
2K x 9
Mode
Master
Slave
Device
HD121L
HD125L
Key Features:
•
•
•
•
•
•
•
•
•
•
•
Industry leading asynchronous Dual-Port Static RAM (up to 15ns)
Simultaneous memory access through two ports
TTL compatible; 5V power supply
Supports Interrupt arbitration schemes
Bus Width can easily expand to over 18 bits by using both MASTER and SLAVE
HD121 with on-chip port arbitration logic
BUSY output flag on HD121; BUSY input flag on HD125
Available packages: 52 – pin Plastic Lead Chip Carrier (PLCC)
(0
°
C to 70
°
C) Commercial operating temperature available for access time of 15ns and above
(-40
°
C to 85
°
C) Industrial operating temperature available for access time of 25ns
Pin-to-pin compatible with conventional dual-port devices including IDT 70121, 70125
Product Description:
HBA’s Asynchronous Dual-Port (ADP I) Static RAM offers industry leading 0.25um process technology and 2K x 9 memory
configuration. Both devices support two memory ports with independent control, address, and I/O pins that enable simultaneous,
asynchronous access to any location in memory. System designer has full flexibility of implementing deeper and wider memory
using the depth and width expansion features.
The HD121 is a stand alone 18K-bit Dual-Port Static RAM or as a “MASTER” Dual-Port Static RAM with HD125 as a
“SLAVE” Dual-Port Static RAM in 18-bit-or-more bus width application. No additional discrete logic is required when using the
MASTER/SLAVE configuration to provide bus width expansion.
These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such
as data communication, telecommunication, multiprocessing, test equipment, network switching, etc.
5HD091A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
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HD121/125
ADP SRAM I
Block D iagram of Asynchronous D ual Port Static R AM
2K X 9
OE
L
CE
L
R /
W
L
OE
R
CE
R
R /W
R
I/O
0 -8 L
I/O
Control
I/O
Control
I/O
0 -8 R
BUSY
L
(1,2)
BUSY
R
(1,2)
A
10 L
A
0 L
Address
Decoder
SRAM
Address
Decoder
A
10 R
A
0 R
OE
L
CE
L
R /
W
L
Arbitration
and
Interrupt
Logic
OE
R
CE
R
R / W
R
(2)
IN T
L
IN T
R
(2)
NOTES:
1.
2.
HD121 MASTER mode: BUSY is open drain. HD125 SLAVE mode: BUSY is input
Open drain output: requires pull-up resistor of 270Ω
Figure 1. Device Architecture
__________
__________
5HD091A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
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HD121/125
ADP SRAM I
BUSY
R
49
BUSY
L
R/W
R
R/W
L
INT
R
48
INT
L
Index
7
6
5
4
3
2
1
52
51
50
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
A
10R
47
46
45
44
43
42
A
10L
OE
L
CE
R
CE
L
V
CC
A
0L
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
8R
I/O
7R
PLCC-52 (Drw No: J-02A; Order code: J)
Top View
41
40
39
38
37
36
35
34
27
28
29
30
31
32
33
GND
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
Figure 2. Device Pin-Out
I/O
6R
5HD091A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
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PRELIMINARY
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HD121/125
ADP SRAM I
Left Port
_____
Right Port
CE
R
BUSY
R
INT
R
OE
R
A
0R-10R
I/O
0R –8R
Vcc
_____
______
__________
_____
Name
Chip Enable
Read / Write Enable
Busy Flag
Interrupt Flag
Output Enable
Address
Data Inputs/Outputs
Power
Ground
Symbol
Rating
Terminal Voltage with
respect to GND
Temperature Under Bias
Storage Temperature
DC Output Current
Com & Ind
-0.5 to + 7.0
-55 to +125
-60 to +150
50
Unit
V
°
CE
L
BUSY
L
INT
L
OE
L
A
0L-10L
I/O
0L-8R
GND
_____
______
__________
R/W
L
____
R/W
R
____
V
TERM
T
BIAS
T
STG
I
OUT
NOTES:
C
C
°
mA
Table 1. Pin Descriptions
Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended
period of operation is outside this range. Standard operation should fall within the Recommended
Operating Conditions
.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Commercial Temperature
Min.
4.5
0
2.2
-0.5
0
-
-
2.4
-
Industrial Temperature
Min.
4.5
0
2.2
-0.5
-40
-
-
2.4
-
Typ.
5.0
0
-
-
-
-
-
-
-
Max.
5.5
0
6.0
0.8
70
10
10
-
0.4
Typ.
5.0
0
-
-
-
-
-
-
-
Max.
5.5
0
6.0
0.8
85
10
10
-
0.4
Unit
Recommended Operating Conditions
V
CC
GND
Supply Voltage Com’l/Ind’l
Supply Voltage
Input High Voltage Com’l/Ind’l
Input Low Voltage Com’l/Ind’l
Operating Temperature
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, IOH=-4mA
Output Logic “0” Voltage, IOL = 4mA
V
V
V
V
°
V
IH
V
IL
T
A
I
LI
(1)
I
LO
V
OH
V
OL
C
DC Electrical Characteristics
µA
µA
V
V
Capacitance at 1.0MHz Ambient Temperature (25°C)
Symbol
Parameter
Input Capacitance
C
IN(2)
Output Capacitance
C
OUT(2)
NOTES:
Conditions
(3)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
1. At Vcc < 2.0V, input leakage is undefined.
2. This parameter is determined by device characterization but is not production tested.
3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V.
5HD091A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
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HD121/125
ADP SRAM I
Power Consumption
Symbol
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current (Both
Ports – TTL Level
Inputs)
Standby Current (One
Port – TTL Level Inputs)
Full Standby Current
(Both Ports – All CMOS
Level Inputs)
Standby Current (One
Port – All CMOS Level
Inputs)
_____
Conditions
CE = V
IL
, Outputs Disabled,
f=f
MAX
_____
Temp
C
I
C
I
C
I
C
I
C
I
HD121L15
HD125L15
Typ.
Max.
240
-
45
-
165
-
5
-
160
-
135
-
30
-
80
-
0.2
-
70
-
HD121L25
HD125L25
Typ.
135
135
30
30
80
80
0.2
0.2
70
70
Unit
Max.
220
260
45
65
145
175
5
mA
5
140
170
mA
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
CE
L
= CE
R
= V
IH
, f=f
MAX
CE
A
= V
IL
and CE
B
= V
IH
Active Port Outputs Disabled,
f=f
MAX
Both Ports CE
L
and CE
R
> Vcc
– 0.2V, V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
_____
_____
_____
_____
_____
mA
CE
A
< 0.2V and CE
B
> Vcc –
0.2V, Active Port Outputs
Disabled, f=f
MAX
_____
_____
Power Consumption
Symbol
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current (Both
Ports – TTL Level
Inputs)
Standby Current (One
Port – TTL Level Inputs)
Full Standby Current
(Both Ports – All CMOS
Level Inputs)
Standby Current (One
Port – All CMOS Level
Inputs)
NOTES:
1.
2.
3.
4.
At f=f
MAX
, address and control lines, except Output Enable, are cycling at the maximum frequency read cycle of 1/trc, and using AC Test Conditions of input level of GND
to 3V.
f = 0 means no address or control lines change.
Vcc = 5V, tA = +25C for Typ and is not production tested. Vcc dc = 100mA (Typ)
Port A and B can be either left or right port. If Port A is left port, Port B is right port. If Port A is right port, Port B is left port.
_____
Conditions
CE = V
IL
, Outputs Disabled,
f=f
MAX
_____
Temp
C
I
C
I
C
I
C
I
C
I
HD121L35
HD125L35
Typ.
Max.
210
-
45
-
135
-
5
-
130
-
135
-
30
-
80
-
0.2
-
70
-
HD121L55
HD125L55
Typ.
135
-
30
-
80
-
0.2
-
70
-
Unit
Max.
205
-
45
-
130
-
5
mA
-
125
-
mA
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
CE
L
= CE
R
= V
IH
, f=f
MAX
CE
A
= V
IL
and CE
B
= V
IH
Active Port Outputs Disabled,
f=f
MAX
Both Ports CE
L
and CE
R
> Vcc
– 0.2V, V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
_____
_____
_____
_____
_____
mA
CE
A
< 0.2V and CE
B
> Vcc –
0.2V, Active Port Outputs
Disabled, f=f
MAX
_____
_____
5HD091A
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject
to change without notice.
PRELIMINARY
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