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IDT79RV4700-100-DP

Description
64-Bit RISC Microprocessor
File Size533KB,25 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

IDT79RV4700-100-DP Overview

64-Bit RISC Microprocessor

64-Bit RISC Microprocessor
IDT79R4700
Features
True 64-bit microprocessor
– 64-bit integer operations
– 64-bit floating-point operations
– 64-bit registers
– 64-bit virtual address space
High-performance microprocessor
– 260 Dhrystone MIPS at 200MHz
– 100 peak MFLOP/s at 200MHz
– Two-way set associative caches
– Simple 5-stage pipeline
High level of integration
– 64-bit, 200 MHz integer CPU
– 64-bit floating-point unit
– 16KB instruction cache
– 16KB data cache
– Flexible MMU with large, fully associative TLB
Low-power operation
– 3.3V power supply, for the “RV” part
– 5V power supply, for the “R” part
– Dynamic power management
– Standby mode reduces internal power
Fully software & pin-compatible with 40
XX
Processor Family
Available in 179-pin PGA or 208-pin QFP
Available at 80-200MHz, with mode bit dependent output
clock frequencies
64GB physical address space
Processor family for a wide variety of embedded
applications
– LAN switches
– Routers
– Color printers
Description
The IDT79R4700 64-bit RISC Microprocessor is both software and
pin-compatible with the R4
XXX
processor family. With 64-bit processing
capabilities, the R4700 provides more computational power and data
movement bandwidth than is delivered to typical embedded systems by
32-bit processors.
The R4700 is upwardly software compatible with the IDT79R3000
microprocessor family, including the IDTRISController
79R3051
,
R3052
, R3041
, R3081
as well as the R4640
, R4650
, RC64474/
475
and R5000
. An array of development tools facilitates rapid
development of R4700-based systems, allowing a variety of customers
access to the MIPS Open Architecture philosophy.
Block Diagram
Data Set A
Store Buffer
SysAD
Instruction Select
Write Buffer
Read Buffer
Data Set B
DBus
Control
Tag
Floating-point
Register File
Unpacker/Packer
Floating-point
Add/Sub/Cvt/Div/Sqrt
Integer Divide
Floating-point Control
Data Tag A
DTLB Physical
Data Tag B
Instruction Set A
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
IBus
AuxTag
Instruction Register
Instruction Set B
Load Aligner
Joint TLB
Integer Register File
Integer/Address Adder
Coprocessor 0
DVA
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
PC Incrementer
System/Memory
Control
IVA
Branch Adder
Instruction TLB Virtual
Program Counter
Integer Control
Floating-point/Integer
Multiply
Phase Lock Loop, Clocks
The IDT logo is a trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Inte-
grated Device Technology, Inc.
1 of 25
©
2008 Integrated Device Technology, Inc.
December 5, 2008
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