256KB AND 512KB SECONDARY
CACHE MODULES FOR THE
PowerPC™
Integrated Device Technology, Inc.
IDT7MPV6253
IDT7MPV6255/56
FEATURES
• For CHRP based PowerPC™ systems.
• Asynchronous and pipelined burst SRAM options in the
same module pinout
• Low-cost, low-profile card edge module with 178 leads
• Uses Burndy Computerbus™ connector, part number
ELF182KSC-3Z50
• Operates with external PowerPC CPU speeds up to
66MHz
• Separate 5V (±5%) and 3.3V (+10/-5%) power supplies
• Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
• Presence Detect output pins allow the system to deter-
mine the particular cache configuration.
x 8 asynchronous static RAMs and the IDT7MPV6255/56 use
IDT’s 71V432 32K x 32 pipelined synchronous burst static
RAMs in plastic surface mount packages mounted on a
multilayer epoxy laminate (FR-4) board. In addition, each of
the modules uses the IDT 71216 16K x 15 Cache-Tag static
RAM and IDT FCT logic. Extremely high speeds are achieved
using IDT’s high-reliability, low cost CMOS technology.
The low profile card edge package allows 178 signal leads
to be placed on a package 5.06" long, a maximum of 0.250"
thick and a maximum of 1.08" tall. The module space savings
versus discrete components allows the OEM to design addi-
tional functions onto the system or to shrink the size of the
motherboard for reduced cost.
All inputs and outputs are LVTTL-compatible, and operate
from separate 5V (±5%) and 3.3V (+10/-5%) power supplies.
Multiple GND pins and on-board decoupling capacitors en-
sure maximum protection from noise.
DESCRIPTION
The IDT7MPV6253/55/56 modules belong to a family of
secondary caches intended for use with PowerPC CPU-
based systems. The IDT7MPV6253 uses IDT’s 71V256 32K
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6253 – 256KB ASYNCHRONOUS VERSION
A
14
- A
26
ALE
ADDR
A0
ADDR
A1
SRAM OE
1
WE#
0
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
8
13
Latch
13
PD
0
PD
1
PD
2
ADDR
A0
ADDR
A1
SRAM OE
0
DH
0
- DH
7
WE#
4
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
8
PD
3
DL
0
- DL
7
WE#
1
8
DH
8
- DH
15
WE#
5
8
DL
8
- DL
15
WE#
2
8
DH
16
- DH
23
WE#
6
8
DL
16
- DL
23
WE#
3
STANDBY
A
14
- A
26
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK
2
13
8
DH
24
- DH
31
WE#
7
STANDBY
12
8
DL
24
- DL
31
A
2
- A
13
TMATCH
8K x 12
Tag Field
8K x 2
Status
DIRTYOUT
drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc. PowerPC is a trademark of IBM. Computerbus is trademark of Burndy.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
JUNE 1996
DSC-3608/2
1
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6255 – 256KB PIPELINED BURST VERSION
WE#
0
WE#
1
WE#
2
WE#
3
CLK
1
CLK
0
WE#
4
WE#
5
WE#
6
WE#
7
SRAM OE#0
SRAM ADS#0
CNT EN#0
STANDBY
BURST MODE
A
14
- A
28
15
32K x 32
Pipelined
Burst
SRAM
32
DH
0
-
31
32K x 32
Pipelined
Burst
SRAM
32
DL
0
-
31
PD
0
PD
1
PD
2
PD
3
A
14
- A
26
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK
2
13
12
A
2
- A
13
TMATCH
8K x 12
Tag Field
8K x 2
Status
DIRTYOUT
drw 02
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CC3
V
CC5
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Input High Voltage
Min.
3.14
4.75
0
2.2
Typ.
3.3
5.0
0
—
—
Max.
3.6
5.25
0.0
V
CC
+ 0.3
0.8
Unit
V
V
V
V
V
tbl 01
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Value
–0.5 to +4.6
0 to +70
–10 to +85
–55 to +125
50
Unit
V
°C
°C
°C
mA
V
TERM
Terminal Voltage with Respect
for V
CC3
to GND
T
A
T
BIAS
T
STG
I
OUT
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current
Input Low Voltage –0.5
(1)
NOTE:
1. V
IL
= –1.0V for pulse width less than 5ns, once per cycle.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Power Plane
V
CC3
V
CC5
Ambient Temperature
0°C to +70°C
0°C to +70°C
GND
0V
0V
V
CC
3.3V +10/-5%
5.0V
±
5%
tbl 02
NOTE:
tbl 03
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
SRAM ACCESS TIMES
Module Speed
66MHz
Asych
15ns
Burst
(1)
8.5ns
Tag
10ns
tbl 04
NOTE:
1. Burst SRAMs are measured by Clock to Data Out (t
CD
).
2
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6256 – 512KB PIPELINED BURST VERSION
WE#
0
WE#
1
WE#
2
WE#
3
CLK
1
WE#
4
WE#
5
WE#
6
WE#
7
CLK
0
SRAM OE#0
SRAM ADS#0
CNT EN#0
STANDBY
BURST MODE
A
13
- A
28
16
32K x 32
Pipelined
Burst
SRAM
32
WE#
0
WE#
1
WE#
2
WE#
3
CLK
1
WE#
4
WE#
5
WE#
6
WE#
7
CLK
0
32K x 32
Pipelined
Burst
SRAM
32
DH
0
-
31
32K x 32
Pipelined
Burst
SRAM
32K x 32
Pipelined
Burst
SRAM
DH
0
-
31
32
32
DL
0
-
31
SRAM OE#1
SRAM ADS#1
CNT EN#1
STANDBY
BURST MODE
DL
0
-
31
A
13
- A
26
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK
2
14
12
A
1
- A
12
TMATCH
16K x 12
Tag Field
16K x 2
Status
PD
0
PD
1
PD
2
PD
3
DIRTYOUT
drw 03
CAPACITANCE (IDT7MPV6253 )
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
Parameter
(1)
C
IN1
Input Capacitance
(Address)
Input Capacitance
C
IN2
(ADDR
0-1
)
C
IN3
Input Capacitance
(OE#)
Input Capacitance
C
IN4
(WE#, TWE#)
C
I/O
I/O Capacitance
Condition
V
IN
= 0V
V
IN
= 0V
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
Max.
15
25
45
8
10
Unit
pF
pF
pF
pF
pF
tbl 05
CAPACITANCE (IDT7MPV6255/56 )
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
Parameter
(1)
C
IN1
Input Capacitance
(Address)
Input Capacitance
C
IN2
(ADDR
0-1
)
C
IN3
Input Capacitance
(OE#)
Input Capacitance
C
IN4
(WE#, TWE#)
C
I/O
I/O Capacitance
Condition
V
IN
= 0V
V
IN
= 0V
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
Max.
20
—
15
8
10/20
Unit
pF
pF
pF
pF
pF
tbl 06
NOTES:
1. These parameters are guaranteed by design but not tested.
NOTES:
1. These parameters are guaranteed by design but not tested.
3
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
(1)
GND
PD
1
PD
3
DH
31
DH
29
DH
27
DH
25
V
CC3
SRAM WE
3
DH
23
DH
21
DH
18
GND
DH
16
SRAM WE
2
DH
14
DH
13
VCC
5
DH
10
DH
8
SRAM WE
1
DH
6
VCC
3
DH
4
GND
CLK
0
GND
DH
1
SRAM WE0
DL
31
DL
30
GND
DL
29
DL
27
DL
25
V
CC5
SRAM WE
7
DL
23
DL
21
DL
19
GND
DL
17
SRAM WE
6
DL
15
DL
13
GND
DL
10
DL
8
SRAM WE
5
DL
6
V
CC3
DL
5
DL
2
GND
(1)
CLK
3
GND
(1)
CLK
4
GND
SRAM WE
4
(3,4)
SRAM ALE
V
CC3
(3,4)
ADDR
1
(1)
RSVD
(2)
SRAM CNT EN
0
(2,3)
SRAM CNT EN
1
A
27
A
24
A
22
A
20
GND
A
18
A
16
A
15
A
14
V
CC3
A
10
A
8
A
6
GND
A
4
A
2
(2,3)
A
1
BURST MODE
V
CC5
TAG VALID
TAG WE
STANDBY
DIRTYOUT
GND
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
167
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
GND
PD
0
PD
2
DH
30
DH
28
DH
26
DH
24
V
CC3
DP
3
(1)
DH
22
DH
20
DH
19
GND
DH
17
DP
2
(1)
DH
15
DH
12
V
CC5
DH
11
DH
9
DP
1
(1)
DH
7
V
CC3
DH
5
DH
3
DH
2
DH
0
DP
0
(1)
GND
CLK
1
GND
DL
28
DL
26
DL
24
DP
7
(1)
V
CC5
DL
22
DL
20
DL
18
DL
16
GND
DP
6
(1)
DL
14
DL
12
DL
11
GND
DL
9
DP
5
(1)
DL
7
DL
4
V
CC3
DL
3
DL
1
DL
0
GND
CLK
2
(TAG)
GND
DP
4
(1)
SRAM OE
0
SRAM OE
1
(3)
VCC
3
ADDR
0
(3,4)
RSVD
(1)
SRAM ADS
0
(2)
SRAM ADS
1
(2,3)
A
28
A
26
A
25
A
23
GND
A
21
A
19
A
17
A
13
V
CC3
A
12
A
11
A
9
GND
A
7
A
5
A
3
A
0
(1)
V
CC5
TAG CLR
TAG MATCH
TAG OE
DIRTYIN
GND
PIN NAMES
A
0
– A
28
ADDR
0
- ADDR
1
CLK
0
- CLK
4
DH
0
- DH
31
DL
0
- DL
31
PD
0
– PD
3
SRAM ADS
0
-
SRAM ADS
1
SRAM ALE
SRAM CNT EN
1
SRAM OE
0
-
SRAM OE
1
SRAM WE
0
-
SRAM WE
1
BURST MODE
TAG CLR
TAG MATCH
TAG VALID
TAG OE
TAG WE
DIRTYIN
DIRTYOUT
STANDBY
V
CC3
V
CC5
GND
NC
RSVD
Burst Mode: 0=Linear, 1=Interleaved
Tag Clear
Tag Match
Tag Valid
Tag Output Enable
Tag Write Enable
Dirty Input Bit
Dirty Output Bit
Stand By Mode
3.3 Volt Power Supply
5 Volt Power Supply
Ground
No Connect
Reserved
tbl 07
Address Inputs
Address Inputs (Asynchronous SRAMs only)
Clock Inputs
High Order Cache Data
Low Order Cache Data
Presence Detect Pins
SRAM Address Strobe
SRAM Address Latch Enable
SRAM CNT EN
0
- SRAM Control Enable
SRAM Output Enable
SRAM Write Enable
PRESENCE DETECT TABLE
PD
3
NC
NC
GND
GND
PD
2
NC
GND
GND
NC
PD
1
NC
NC
NC
PD
0
NC
NC
NC
Module
No cache present
IDT7MPV6253
IDT7MPV6255
IDT7MPV6256
tbl 08
GND GND
NOTES:
1. These pins are NC (No Connect) on 7MPV6253/55/56.
2. These pins are NC on 7MPV6253.
3. These pins are NC on 7MPV5255.
4. These pins are NC on 7MPV6256.
LOW PROFILE CARD EDGE MODULE
TOP VIEW
drw 04
4
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(V
CC5
= 5.0V
±
5%, V
CC3
= 3.3V
±
10%, T
A
= 0°C to 70°C)
Symbol
|I
LI
|
|I
LI
|
|I
LO
|
V
OL
V
OH
I
CC3
I
CC5
I
SB3
I
SB31
Parameter
Input Leakage Current
(Address)
Input Leakage Current
(Data and Control)
Output Leakage Current
Output Low Voltage
Output HighVoltage
Operating 3.3V Power
Supply Current
Operating 5V Power
Supply Current
Standby 3.3V Power
Supply Current
Full Standby 3.3V Power
Supply Current
Standby 5V Power
Supply Current
Test Condition
V
CC5
= Max, V
IN
= GND to V
CC
V
CC3
= Max
V
CC5
= Max, V
IN
= GND to V
CC
V
CC3
= Max
V
OUT
= 0V to V
CC3
,
V
CC3
= Max.
I
OL
= 8mA, V
CC3
= Min.
I
OH
= –4mA, V
CC3
= Min.
V
CC3
= Max., STANDBY
≤
V
IL
,
f = f
MAX
, Outputs Open
V
CC5
= Max., STANDBY
≤
V
IL
,
f = f
MAX
, Outputs Open
V
CC3
= Max., STANDBY
≥
V
IH
,
f = f
MAX
, Outputs Open
V
CC3
= Max., STANDBY
≥
V
CC3
- 0.2V, f = 0,
V
IN
≤
0.2V or V
IN
≥
V
CC3
- 0.2V,
Outputs Open
V
CC5
= Max., STANDBY
≥
V
IH
f = f
MAX,
Outputs Open
Min.
—
—
—
—
2.4
—
—
—
—
’53
Max.
20
10
10
0.4
—
1000
290
100
30
’55
Max.
30
10
10
0.4
—
500
290
100
30
’56
Max.
50
20
20
0.4
—
590
290
190
50
Unit
µA
µA
µA
V
V
mA
mA
mA
mA
I
SB5
—
30
30
30
mA
tbl 09
AC TEST CONDITIONS – 3.3V POWER SUPPLY
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
tbl 10
+3.3V
320
Ω
DATA
OUT
350
Ω
30pF*
DATA
OUT
350
Ω
+3.3V
320
Ω
5pF*
*including scope and jig capacitances
Figure 1. Output Load
drw 05
*including scope and jig capacitances
Figure 2. Output Load
(for t
OHZ
, t
CHZ
, t
OLZ
and t
CLZ
)
drw 06
5
51mcu
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