532MA1417M000DGR datasheet, PDF

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532MA1417M000DGR: DescriptionOscillator; CategoryPassive components oscillator; File Size230KB，12 Pages; ManufacturerSilicon Laboratories Inc

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532MA1417M000DGR Overview

Oscillator

532MA1417M000DGR Parametric

Parameter Name	Attribute value
Reach Compliance Code	unknown
Base Number Matches	1

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Si532

EVISION

U A L

R E Q U E N C Y

R Y S TA L

S C I L L A T O R

(XO )

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

Two selectable output frequencies

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a low jitter clock at high frequencies. The Si532 is

available with any-rate output frequency from 10 to 945 MHz and select

frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is

required for each output frequency, the Si532 uses one fixed crystal

frequency to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The Si532 IC

based XO is factory configurable for a wide variety of user specifications

including frequency, supply voltage, output format, and temperature stability.

Specific configurations are factory programmed at time of shipment, thereby

eliminating long lead times associated with custom oscillators.

CLK–

CLK+

(LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

(CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

Rev. 1.1 6/07

Si532

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