Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope using
’trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in switched mode
power supplies and general purpose
switching applications.
IRFZ48N
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 10 V
MAX.
55
64
140
175
16
UNIT
V
A
W
˚C
mΩ
PINNING - TO220AB
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
20
64
45
210
140
175
UNIT
V
V
V
A
A
A
W
˚C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
in free air
TYP.
-
60
MAX.
1.1
-
UNIT
K/W
K/W
February 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
(BR)GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
Gate-source breakdown
voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 55 V; V
GS
= 0 V;
V
GS
=
±10
V; V
DS
= 0 V
I
G
=
±1
mA;
V
GS
= 10 V; I
D
= 25 A
T
j
= 175˚C
T
j
= 175˚C
T
j
= 175˚C
MIN.
55
50
2
1
-
-
-
-
-
16
-
-
TYP.
-
-
3.0
-
-
0.05
-
0.02
-
-
12
-
IRFZ48N
MAX.
-
-
4.0
-
4.4
10
500
1
20
-
16
30
UNIT
V
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
g
fs
C
iss
C
oss
C
rss
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
PARAMETER
Forward transconductance
Input capacitance
Output capacitance
Feedback capacitance
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
CONDITIONS
V
DS
= 25 V; I
D
= 25 A
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
8
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP.
39
2200
500
200
-
-
-
18
35
45
30
3.5
4.5
7.5
MAX.
-
2900
600
270
85
19
37
26
85
60
45
-
-
-
UNIT
S
pF
pF
pF
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
I
D
= 50 A; V
DD
= 44 V; V
GS
= 10 V
V
DD
= 30 V; I
D
= 25 A;
V
GS
= 10 V; R
G
= 10
Ω
Resistive load
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
February 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 65 A; V
GS
= 0 V
I
F
= 65 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
-
-
-
-
-
TYP.
-
-
0.95
1.0
57
0.14
IRFZ48N
MAX.
64
210
1.2
-
-
-
UNIT
A
A
V
V
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 65 A; V
DD
≤
25 V;
V
GS
= 10 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
TYP.
-
MAX.
200
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
20
40
60
80 100
Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
February 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
IRFZ48N
SOAX514
RDS(ON)/mOhm
30
VGS/V =
6
6.5
7
20
8
15
9
10
1000
ID / A
RDS(ON) = VDS/ID
100
tp =
1 us
10 us
100 us
DC
1 ms
25
10
10
10 ms
100 ms
1
5
1
10
VDS / V
55
100
0
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
ID/A
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
100
ID/A
80
1E+01
Zth / (K/W)
BUKX514-55
1E+00
0.5
1E-01
0.2
0.1
0.05
0.02
1E-02
0
T
t
20
60
P
D
t
p
D=
t
p
T
40
Tj/C =
175
25
1E-03
1E-07
1E-05
1E-03
t/s
1E-01
1E+01
0
0
1
2
3
4
5
VGS/V
6
7
8
9
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
100
ID/A
80
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
40
gfs/S
35
30
16
10
8
7.5
VGS/V =
7
6.5
60
6
40
5.5
25
20
15
10
20
5
0
4.5
4
0
2
4
VDS/V
6
8
10
5
0
0
20
40
60
80
100
ID/A
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
February 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
IRFZ48N
2.5
a
BUK959-60
Rds(on) normlised to 25degC
4
3.5
Thousands (pF)
2
3
2.5
2
1.5
1
5
Coss
Crss
100
Ciss
1.5
1
0.5
-100
-50
0
50
Tmb / degC
100
150
200
0
0.01
0.1
1
VDS/V
10
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
VGS(TO) / V
max.
4
typ.
3
min.
2
BUK759-60
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
12
VGS/V
10
VDS = 14V
8
VDS = 44V
5
6
4
1
2
0
-100
-50
0
50
Tj / C
100
150
200
0
0
10
20
30 QG/nC 40
50
60
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Sub-Threshold Conduction
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 50 A; parameter V
DS
100
IF/A
80
1E-01
1E-02
2%
typ
98%
60
Tj/C =
40
175
25
1E-03
1E-04
20
1E-05
0
1E-06
0
0.2
0.4
0
1
2
3
4
5
0.6
0.8
VSDS/V
1
1.2
1.4
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
February 1999
5
Rev 1.000
Power technology
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