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74HC107D,652

Description
74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger SOIC 14-Pin
Categorylogic    logic   
File Size800KB,18 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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74HC107D,652 Overview

74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger SOIC 14-Pin

74HC107D,652 Parametric

Parameter NameAttribute value
Brand NameNexperia
Is it Rohs certified?conform to
MakerNexperia
Parts packaging codeSOIC
package instructionPLASTIC, SO-14
Contacts14
Manufacturer packaging codeSOT108-1
Reach Compliance Codecompliant
Samacsys Confidence2
Samacsys StatusReleased
Samacsys PartID659268
Samacsys Pin Count14
Samacsys Part CategoryIntegrated Circuit
Samacsys Package CategorySmall Outline Packages
Samacsys Footprint NameSO14
Samacsys Released Date2019-11-12 07:41:52
Is SamacsysN
seriesHC/UH
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-K FLIP-FLOP
Humidity sensitivity level1
Number of digits2
Number of functions2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)48 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typeNEGATIVE EDGE
width3.9 mm
minfmax60 MHz
Base Number Matches1
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 — 30 November 2015
Product data sheet
1. General description
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring
individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q
outputs. The reset is an asynchronous active LOW input and operates independently of
the clock input. The J and K inputs control the state changes of the flip-flops as described
in the mode select function table. The J and K inputs must be stable one set-up time prior
to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp
diodes that enable the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
The 74HC107: CMOS levels
The 74HCT107: TTL levels
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC107D
74HCT107D
74HC107DB
74HC107PW
40 C
to +125
C
40 C
to +125
C
SSOP14
TSSOP14
40 C
to +125
C
Name
SO14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
Version
SOT108-1
SOT337-1
Type number
plastic thin shrink small outline package; 14 leads; body SOT402-1
width 4.4 mm

74HC107D,652 Related Products

74HC107D,652 74HC107DB,112 74HCT107D,653 74HCT107D,652 74HC107PW,118 74HC107PW,112 74HC107D,653
Description 74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger SOIC 14-Pin IC FF JK TYPE DUAL 1BIT 14SSOP IC FF JK TYPE DUAL 1BIT 14SO IC FF JK TYPE DUAL 1BIT 14SO IC FF JK TYPE DUAL 1BIT 14TSSOP IC FF JK TYPE DUAL 1BIT 14TSSOP IC FF JK TYPE DUAL 1BIT 14SO
Brand Name Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
Parts packaging code SOIC SSOP1 SOIC SOIC TSSOP TSSOP SOIC
package instruction PLASTIC, SO-14 SSOP, SOP, SOP, TSSOP, TSSOP, PLASTIC, SO-14
Contacts 14 14 14 14 14 14 14
Manufacturer packaging code SOT108-1 SOT337-1 SOT108-1 SOT108-1 SOT402-1 SOT402-1 SOT108-1
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant
series HC/UH HC/UH HCT HCT HC/UH HC/UH HC/UH
JESD-30 code R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
JESD-609 code e4 e4 e4 e4 e4 e4 e4
length 8.65 mm 6.2 mm 8.65 mm 8.65 mm 5 mm 5 mm 8.65 mm
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP
Humidity sensitivity level 1 1 1 1 1 1 1
Number of digits 2 2 2 2 2 2 2
Number of functions 2 2 2 2 2 2 2
Number of terminals 14 14 14 14 14 14 14
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SSOP SOP SOP TSSOP TSSOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) 260 260 260 260 260 260 260
propagation delay (tpd) 48 ns 48 ns 54 ns 54 ns 48 ns 48 ns 48 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.75 mm 2 mm 1.75 mm 1.75 mm 1.1 mm 1.1 mm 1.75 mm
Maximum supply voltage (Vsup) 6 V 6 V 5.5 V 5.5 V 6 V 6 V 6 V
Minimum supply voltage (Vsup) 2 V 2 V 4.5 V 4.5 V 2 V 2 V 2 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm 0.65 mm 1.27 mm 1.27 mm 0.65 mm 0.65 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30 30 30 30
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
width 3.9 mm 5.3 mm 3.9 mm 3.9 mm 4.4 mm 4.4 mm 3.9 mm
minfmax 60 MHz 60 MHz 60 MHz 60 MHz 60 MHz 60 MHz 60 MHz
Is it Rohs certified? conform to - - conform to conform to conform to conform to
Maker Nexperia Nexperia Nexperia - Nexperia Nexperia Nexperia
Base Number Matches 1 - - 1 1 1 1
Samacsys Description - 74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger@en-us 74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger@en-us - 74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger@en-us 74HC(T)107 - Dual JK flip-flop with reset; negative-edge trigger@en-us -
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