AVS
Technology
FEATURES
• Complete DAC and ADC Audio CODEC with headphone
driver.
• Up to 96kHz input sampling frequencies for ADC/DAC
• Selectable DAC De-emphasis Filter.
• Selectable ADC High Pass Filter
• Programmable Audio Data Interface
• I
2
S, Normal, Left justified or DSP data for ADC/DAC
• 16,18, 20 and 24-bit input data resolution
• System clock: 64fs, 96fs,128fs, 192fs, 256fs or 384fs
• 250fs and 272fs system clock for USB application
• Master or Slave Clocking mode
• Regular audio or USB mode audio
• 2 or 3-wire software control interface selectable by external
pin.
• 2 channel microphone or line inputs
• Programmable power down features to conserve power
AV2722
AUDIO CODEC WITH HEADPHONE DRIVER
AND PROGRAMMABLE SAMPLE RATES
DESCRIPTION
The AV2722 is a mixed signal CMOS monolithic device which
is a low cost audio CODEC designed with a built-in
headphone driver. It supports regular audio or USB mode
audio and is therefore ideal for portable MP3 audio and
speech players and recorders. It can also be used for mini-
disk, CD-RW machines.
Stereo line audio inputs with programmable gain are provided
A microphone bias voltage output is also provided which
makes the AV2722 ideal for an electret type microphone.
For the multi-bit signal delta DAC, 64X oversampling digital
interpolation filter is used with programmable de-emphasis,
volume control, and sampling rate selection features. The
DAC supports I2S, Normal, Left justified or DSP data with 16,
18, 20 and 24-bit resolution. Sampling rates from 8KHz to 192
KHz are supported. At the DAC output, stereo headphone
drivers are built in for driving headphones.
For the multi-bit delta-sigma ADC, programmable gain
are provided at the input. state of the art decimation filter is
used to down-sample the received signal and finally a
selectable high pass filter is used to reduce un-wanted low
frequency noise. The digital audio serial output can be
programmed at various formats similar to the DAC input.
GENERAL
• 2.7-volt to 3.6-volt Power Supply range (TBD)
• 28-pin SSOP package
APPLICATIONS
• Low cost, CD-quality consumer audio equipment
• Portable MP3 Players and Recorders
ADVANCE PRODUCT INFORMATION.
AVS RESERVES THE RIGHT TO MODIFY THIS PRODUCT
WITHOUT NOTICE.
XCK
VDD
VDDH
VDDA
D
R
A
FT
LOW
PASS
FILTER
LOW
PASS
FILTER
HEADPHONE
DRIVER
HEADPHONE
DRIVER
GAIN
CONTROL
GAIN
CONTROL
CLOCK GENERATOR
HPDET
AOUTL
HOUTL
AOUTR
HOUTR
VCM
HPVR
AINL
AINR
MICBIAS
AUDIO
DIGITAL AUDIO I/O INTERFACE
SDI
SFDA
SERIAL
INPUT
PORT
INTERPOLATION
DIGITAL
FILTER
MULTI-LEVEL
DELTA-SIGMA
MODULATOR
DAC
DAC
SC
SFAD
VOLUME CONTROL
AUDIO
SERIAL
OUTPUT
PORT
HIGH
PASS
FILTER
DECIMATION
DIGITAL
FILTER
MULTI-LEVEL
DELTA-SIGMA
MODULATOR
ADC
ADC
SDO
2 OR 3 WIRE SERIAL COMMAND PORT
SDA SCL
CSB
MODE
RS/
VSS
VSSH
VSSA
VSSA
AV2722 BLOCK DIAGRAM
AVS Technology Inc.
4110 Clipper Ct., Fremont CA94538
Tel: (510) 353-0848
Fax: (510) 353-0856
1-29
January 22, 2004
AV2722 (Preliminary)
PIN CONFIGURATION
VDD
SC
SDI
SFDA
SDO
SFAD
HPVR
VDDH
HOUTL
HOUTR
VSSH
AOUTL
AOUTR
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AV2722
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
XCK
RS/
SCL
SDA
CSB
MODE
HPDET
AINL
AINR
MICBIAS
VCM
VSSA
VSSA
ORDERING INFORMATION
PRODUCT
AV2722
PACKAGE
28-pin SSOP
TEMPERATURE
RANGE
-25 TO +85
o
C
2-29
January 22, 2004
AV2722 (Preliminary)
PIN ASSIGNMENTS
Pin No. Pin Name
1
2
3
4
VDD
SC
SDI
SFDA
Supply
Type
Description
Power supply for digital circuits
DAC serial input data bit clock. It is input for slave mode and output
for master mode.
DAC serial input data. It can be in normal, left justified, i2s, or DSP
type
DAC sample rate clock. It is input for slave mode and output for mas-
ter mode. For normal or left-justified type SDI data input, a high in
SFDA indicates left channel data, a low in SFDA indicates right chan-
nel data. For I2S type, a low in SFDA indicates left channel data, a
high in SFDA indicates right channel data.For DSP mode, a”sync”
pulse in SFDA is followed by two data words, left channel data is fol-
lowed by right channel data.
ADC serial output data. It can be in normal, left justified, i2s, or DSP
type.
ADC sample rate clock. It is input for slave mode and output for mas-
ter mode. For normal or left-justified type SDO data output, a high in
SFAD indicates left channel data, a low in SFAD indicates right chan-
nel data. For I2S type, a low in SFAD indicates left channel data, a
high in SFAD indicates right channel data. For DSP mode, a”sync”
pulse in SFAD is followed by two data words, left channel data is fol-
lowed by right channel data.
Voltage reference for CAPLESS headphone connection..
Power supply for headphone circuits.
Left channel headphone output.
Right channel headphone output.
Ground for headphone circuits.
Left channel audio line output.
Right channel audio line output.
Power supply for analog circuits.
Ground for analog circuits.
Ground for analog circuits
Analog circuits common mode reference.
Microphone bias.
Right channel line/microphone input.
Digital Input/Output
Digital Input
Digital Input/Output
5
6
SDO
SFAD
Digital Output
Digital Input/Output
7
8
9
10
11
12
13
14
15
16
17
18
19
HPVR
VDDH
HOUTL
HOUTR
VSSH
AOUTL
AOUTR
VDDA
VSSA
VSSA
VCM
MICBIAS
AINR
Analog Output
Supply
Analog Output
Analog Output
Ground
Analog Output
Analog Output
Supply
Ground
Ground
Analog output
Analog Output
Analog Input
3-29
January 22, 2004
AV2722 (Preliminary)
Pin No. Pin Name
20
21
AINL
HPDET
Type
Analog Input
Digital Input
Description
Left channel line/microphone input
Headphone is plugged in or not plugged in indicator. The polarity of
this signal can be inverted or not inverted, which is controlled by pro-
gramming bit HPDETMODE (creg4[2], address 04 hex), a logic “low”
inverts the polarity of HPDET into the chip.
I2C or MPU control interface selection. If MODE is logic “high”, the
chip is using MPU for chip programming. If MODE is logic “low”, the
chip is using I2C for chip programming. MODE can be no-connect
for MPU control due to the internal “pullup” resistor.
3-wire MPU chip select, active low.
3-wire MPU data input /output or 2-wire I2C data input/output
3-wire MPU clock input /2-wire I2C clock input
Active low chip reset
Chip clock input. The clock rate of XCK depends on the audio sam-
pling rate, regular audio or USB audio.
Ground for digital circuits
22
MODE
Digital Input
23
24
25
26
27
28
CSB
SDA
SCL
RS/
XCK
VSS
Digital Input
Digital Input/Output
Digital Input
Digital Input
Digital Input
Ground
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuits is manufactured on a CMOS process. It can be damaged by ESD. AVS recommends that all integrated
circuits be handled with appropriate ESD precautions. Improper handling and installation procedures can cause damage to the
device.
4-29
January 22, 2004
AV2722 (Preliminary)
XCK SYSTEN CLOCK REQUIREMENT
The system clock (XCK at pin 27) for the AV2722 supports audio sampling rates from 64fs to 384fs for regular type
audio, where fs is the audio sampling frequency (SFDA /SFAD), typically 8KHz, 44.1KHz, 48KHz, 96KHz, or
192KHz. For USB type audio, SFDA /SFAD is either 250fs or 272fs. XCK is used to operate the digital interpolation
filter and the delta-sigma modulator. By using the two-wire (I2S) or 3-wire (MPU type) serial command port, user
can program the chip to accept different clock frequency under different sampling rate.
Sampling Rate
XCK Clock Frequency (MHz) For Regular Mode
64fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.288
96fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
18.432
128fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
11.289
12.288
24.576
192fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
16.934
18.432
36.864
256fs
12.288
12.288
12.288
12.288
11.289
11.289
11.289
11.289
N/A
N/A
49.152
384fs
18.432
18.432
18.432
18.432
16.934
16.934
16.934
16.934
N/A
N/A
73.728
ADC
48KHz
48KHz
8KHz
8KHz
44.1KHz
44.1KHz
8KHz
8KHz
88.2KHz
96KHz
OFF
DAC
48KHz
8KHz
48KHz
8KHz
44.1KHz
8KHz
44.1KHz
8KHz
88.2Khz
96KHz
192KHz
Sampling Rate
XCK Clock Frequency (MHz) For USB Mode
250fs
12
12
12
12
12
N/A
N/A
N/A
N/A
N/A
N/A
272fs
N/A
N/A
N/A
N/A
N/A
12
12
12
12
12
12
ADC
48KHz
48KHz
8KHz
8KHz
96KHz
44.1KHz
44.1KHz
44.1KHz
8KHz
8KHz
88.2KHz
DAC
48KHz
8KHz
48KHz
8KHz
96KHz
44.1KHz
8KHz
8KHz
44.1KHz
8KHz
88.2KHz
5-29
January 22, 2004
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