IS82C37A datasheet, PDF - EEWORLD Datasheet

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IS82C37A: Description4 CHANNEL(S), 8 MHz, DMA CONTROLLER, PQCC44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size150KB，23 Pages; ManufacturerHarris; Websitehttp://www.harris.com/

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IS82C37A Overview

4 CHANNEL(S), 8 MHz, DMA CONTROLLER, PQCC44

IS82C37A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Harris
package instruction	QCCJ, LDCC44,.7SQ
Reach Compliance Code	unknow
Address bus width	16
Bus compatibility	80C286; 80286; 80186; 80C86; 8086; 80C88; 8088; 8085; Z80; NSC800
maximum clock frequency	8 MHz
External data bus width	8
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
Number of DMA channels	4
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
Maximum slew rate	16 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	DMA CONTROLLER

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S E M I C O N D U C T O R

82C37A

CMOS High Performance

Programmable DMA Controller

Description

The 82C37A is an enhanced version of the industry standard

8237A Direct Memory Access (DMA) controller, fabricated

using Harris’ advanced 2 micron CMOS process. Pin

compatible with NMOS designs, the 82C37A offers

increased functionality, improved performance, and

dramatically reduced power consumption. The fully static

design permits gated clock operation for even further

reduction of power.

The 82C37A controller can improve system performance by

allowing external devices to transfer data directly to or from

system memory. Memory-to-memory transfer capability is

also provided, along with a memory block initialization fea-

ture. DMA requests may be generated by either hardware or

software, and each channel is independently programmable

with a variety of features for ﬂexible operation.

The 82C37A is designed to be used with an external

address latch, such as the 82C82, to demultiplex the most

signiﬁcant 8-bits of address. The 82C37A can be used with

industry standard microprocessors such as 80C286, 80286,

80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and

others. Multimode programmability allows the user to select

from three basic types of DMA services, and reconﬁguration

under program control is possible even with the clock to the

controller stopped. Each channel has a full 64K address and

word count range, and may be programmed to autoinitialize

these registers following DMA termination (end of process).

March 1997

Features

• Compatible with the NMOS 8237A

• Four Independent Maskable Channels with Autoinitial-

ization Capability

• Cascadable to any Number of Channels

• High Speed Data Transfers:

- Up to 4MBytes/sec with 8MHz Clock

- Up to 6.25MBytes/sec with 12.5MHz Clock

• Memory-to-Memory Transfers

• Static CMOS Design Permits Low Power Operation

- ICCSB = 10µA Maximum

- ICCOP = 2mA/MHz Maximum

• Fully TTL/CMOS Compatible

• Internal Registers may be Read from Software

Ordering Information

PART NUMBER

5MHz

CP82C37A-5

IP82C37A-5

CS82C37A-5

IS82C37A-5

CD82C37A-5

ID82C37A-5

MD82C37A-5/B

5962-9054301MQA

MR82C37A-5/B

5962-9054301MXA

8MHz

CP82C37A

IP82C37A

CS82C37A

IS82C37A

CD82C37A

ID82C37A

MD82C37A/B

5962-9054302MQA

MR82C37A/B

5962-9054302MXA

12.5MHz

CP82C37A-12

IP82C37A-12

CS82C37A-12

IS82C37A-12

CD82C37A-12

ID82C37A-12

MD82C37A-12/B

5962-9054303MQA

MR82C37A-12/B

5962-9054303MXA

SMD#

44 Pad CLCC

SMD#

-55

C to +125

40 Ld CERDIP

44 Ld PLCC

PACKAGE

40 Ld PDIP

TEMPERATURE

RANGE

C to +70

-40

C to +85

C to +70

-40

C to +85

C to +70

-40

C to +85

-55

C to +125

PKG. NO.

E40.6

N44.65

F40.6

J44.A

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Harris Corporation 1997

File Number

2967.1

4-192

82C37A

Pin Description

SYMBOL

NUMBER

TYPE

DESCRIPTION

: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for

decoupling.

Ground

CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A

operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for

the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for

standby operation.

CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for

CPU communications.

RESET: This is an active high input which clears the Command, Status, Request, and Temporary

registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore

requests. Following a Reset, the controller is in an idle cycle.

READY: This signal can be used to extend the memory read and write pulses from the 82C37A to

accommodate slow memories or I/O devices. READY must not make transitions during its speciﬁed

set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.

HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has

relinquished control of the system busses. HLDA is a synchronous input and must not transition

during its speciﬁed set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising

edge of CLK, during which time HLDA must not transition.

DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request

inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest

priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a

channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is

programmable. RESET initializes these lines to active high. DREQ must be maintained until the

corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused

DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set.

DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data

bus. The outputs are enabled in the Program condition during the I/O Read to output the contents

of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle

when the CPU is programming the 82C37A control registers. During DMA cycles, the most signiﬁ-

cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.

In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during

the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write

the data into the new memory location.

I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-

trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control

signal used by the 82C37A to access data from the peripheral during a DMA Write transfer.

I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-

trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output

control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.

GND

CLK

RESET

READY

HLDA

DREQ0-

DREQ3

16-19

DB0-DB7

21-23

26-30

I/O

IOR

I/O

IOW

I/O

4-194

82C37A

Pin Description

SYMBOL

EOP

NUMBER

(Continued)

TYPE

I/O

DESCRIPTION

END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information

concerning the completion of DMA services is available at the bidirectional EOP pin.

The 82C37A allows an external signal to terminate an active DMA service by pulling the EOP pin

low. A pulse is generated by the 82C37A when terminal count (TC) for any channel is reached,

except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will

be output when the TC for channel 1 occurs.

The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor

to V

When an EOP pulse occurs, whether internally or externally generated, the 82C37A will terminate

the service, and if autoinitialize is enabled, the base registers will be written to the current registers

of that channel. The mask bit and TC bit in the status word will be set for the currently active channel

by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.

A0-A3

32-35

I/O

ADDRESS: The four least signiﬁcant address lines are bidirectional three-state signals. In the Idle

cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or

read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address.

ADDRESS: The four most signiﬁcant address lines are three-state outputs and provide 4-bits of

address. These lines are enabled only during the DMA service.

HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus.

When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made,

the 82C37A issues HRQ. The HLDA signal then informs the controller when access to the system

busses is permitted. For stand-alone operation where the 82C37A always controls the busses, HRQ

may be tied to HLDA. This will result in one S0 state before the transfer.

DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one

has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them

to active low.

ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits

onto the system address bus. AEN can also be used to disable other system bus drivers during DMA

transfers. AEN is active high.

ADDRESS STROBE: This is an active high signal used to control latching of the upper address

byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82.

During block operations, ADSTB will only be issued when the upper address byte must be updated,

thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling

edge of the 82C37A clock.

MEMORY READ: The Memory Read signal is an active low three-state output used to access data

from the selected memory location during a DMA Read or a memory-to-memory transfer.

MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data

to the selected memory location during a DMA Write or a memory-to-memory transfer.

NO CONNECT: Pin 5 is open and should not be tested for continuity.

A4-A7

37-40

HRQ

DACK0-

DACK3

14, 15

24, 25

AEN

ADSTB

MEMR

MEMW

4-195

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