®
ISL5727
Data Sheet
May 2004
FN6082
Dual 10-bit, +3.3V, 260+MSPS, High Speed
D/A Converter
The ISL5727 is a dual 10-bit, 260+MSPS (Mega Samples
Per Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in high
performance communication systems such as base
transceiver stations utilizing 2.5G or 3G cellular protocols.
This device complements the ISL5x57 and ISL5x27 families
of high speed converters, which include 8-, 10-, 12-, and
14-bit devices.
Features
• Low Power . . . . . 233mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• Guaranteed Gain Matching < 0.14dB
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(70dBc to Nyquist, f
S
= 130MSPS, f
OUT
= 10MHz)
• UMTS Adjacent Channel Power = 65dB at 19.2MHz
• EDGE/GSM SFDR = 83dBc at 11MHz in 20MHz Window
Ordering Information
PART
NUMBER
ISL5727IN
ISL5727EVAL1
TEMP.
RANGE
(°C)
-40 to 85
25
PACKAGE
48 Ld LQFP
PKG.
DWG. #
CLOCK
SPEED
• Dual, 3.3V, Lower Power Replacement for AD9763
Q48.7x7A 260MHz
260MHz
Applications
• Cellular Infrastructure - Single or Multi-Carrier: IS-136,
IS-95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
• BWA Infrastructure
Evaluation Platform
Pinout
ISL5727
(LQFP)
TOP VIEW
ID9 (MSB)
NC
QD0 (LSB)
• Quadrature Transmit with IF Range 0–80MHz
• Medical/Test Instrumentation and Equipment
• Wireless Communication Systems
QD1
ID5
ID4
ID6
ID7
ID8
NC
NC
ID3
ID2
ID1
(LSB) ID0
NC
NC
NC
NC
SLEEP
D
VDD
AGND
ICOMP
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
NC
QD2
QD3
QD4
QD5
QD6
QD7
QD8
QD9 (MSB)
CLK
DGND
AGND
QCOMP
REFLO
AGND
FSADJ
IOUTA
IOUTB
QOUTB
QOUTA
REFIO
A
VDD
NC
NC
1
A
VDD
ISL5727
Typical Applications Circuit
ID4
ID5
ID6
ID7
ID8
ID9 (MSB)
NC
NC
NC
NC
QD0 (LSB)
QD1
48 47 46 45 44 43 42 41 40 39 38 37
36
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
CLK 28
9
DGND 27
10 D
VDD
AGND 26
11 AGND
25
12
13 14 15 16 17 18 19 20 21 22 23 24
REFIO
REFLO
AGND
FSADJ
A
VDD
C
4
0.1µF
A
VDD
C
5
0.1µF
ID3
ID2
ID1
(LSB) ID0
NC
NC
NC
NC
DV
PP
C
1
0.1µF
SLEEP
QD2
QD3
QD4
QD5
QD6
QD7
QD8
QD9 (MSB)
R
1
50Ω
C
3
0.1µF
AV
PP
ICOMP
QCOMP
C
2
0.1µF
AV
PP
C
6
0.1µF
R
SET
1.91kΩ
50Ω
R
2
R
3
50Ω
1:1 TRANSFORMER
REPRESENTS
ANY 50Ω LOAD
(50Ω)
IOUT
BEAD
FERRITE
+ C
11
10µF
+3.3V POWER SOURCE
FERRITE
BEAD
+ C
14
10µF
L
2
10µH
AV
PP
(ANALOG POWER PLANE) = +3.3V
C
12
0.1µF
C
13
1µF
L
1
10µH
DV
PP
(DIGITAL POWER PLANE) = +3.3V
C
9
0.1µF
C
10
1µF
(50Ω)
QOUT
2
ISL5727
Functional Block Diagram
NC
NC
NC
NC
(LSB) QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7
QD8
(MSB) QD9
UPPER
5-BIT
DECODER
5 LSBs
INPUT
LATCH
CASCODE
36
SWITCH
MATRIX
36
CURRENT
SOURCE
QOUTA
QOUTB
+
31 MSB
SEGMENTS
QCOMP
SLEEP
CLK
INT/EXT
VOLTAGE
REFERENCE
BIAS
GENERATION
FSADJ
REFIO
REFLO
ICOMP
NC
NC
NC
NC
(LSB) ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
(MSB) ID9
UPPER
5-BIT
DECODER
5 LSBs
+
INPUT
LATCH
CASCODE
36
SWITCH
MATRIX
36
CURRENT
SOURCE
IOUTA
IOUTB
31 MSB
SEGMENTS
3
ISL5727
Pin Descriptions
PIN NO.
11, 19, 26
13, 24
28
27
10
20
14, 23
12, 25
1-4, 29-38,
43-48
15, 22
16, 21
17
18
5-8, 39-42
9
PIN NAME
AGND
A
VDD
CLK
DGND
D
VDD
FSADJ
NC
ICOMP, QCOMP
ID9-ID0, QD9-QD0
IOUTA, QOUTA
IOUTB, QOUTB
REFIO
REFLO
NC
SLEEP
Analog ground.
Analog supply (+2.7V to +3.6V).
Clock input.
Connect to digital ground.
Digital supply (+2.7V to +3.6V).
Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output
current = 32 x V
FSADJ
/R
SET
.
Not internally connected. Recommend no connect.
Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with
a 0.1µF capacitor.
Digital data input ports. Bit 9 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).
Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.
Complementary current outputs of the device. Full scale output current is achieved on the complementary
outputs when all input bits are set to binary 0.
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1µF cap to ground when internal reference is enabled.
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable internal reference.
No connect (NC). Not internally connected. No termination required, may be used for device migration to
higher resolution DACs.
Connect to digital ground or leave floating for normal operation. Connect to DV
DD
for sleep mode.
PIN DESCRIPTION
4
ISL5727
Absolute Maximum Ratings
Digital Supply Voltage DV
DD
to DGND . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AV
DD
to AGND . . . . . . . . . . . . . . . . . . +3.6V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DV
DD
+ 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Offset Drift Coefficient
Full Scale Gain Error, FSE
AV
DD
= DV
DD
= +3.3V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25°C for All Typical Values
T
A
= -40°C TO 85°C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
“Best Fit” Straight Line (Note 8)
(Note 8)
IOUTA (Note 8)
(Note 8)
With External Reference (Notes 2, 8)
With Internal Reference (Notes 2, 8)
-0.5
-0.5
-0.006
-
-3
-3
-
-
-
-
-
-1.6
-0.14
2
(Note 3)
-1.0
-
±0.1
±0.1
-
+0.5
+0.5
+0.006
Bits
LSB
LSB
% FSR
ppm
FSR/°C
% FSR
% FSR
ppm
FSR/°C
ppm
FSR/°C
dB
dB
dB
% FSR
dB FSR
mA
V
0.1
±0.5
±0.5
±50
±100
83
74
73
0.6
0.05
20
-
-
+3
+3
-
-
-
-
-
+1.6
+0.14
22
1.25
Full Scale Gain Drift
With External Reference (Note 8)
With Internal Reference (Note 8)
Crosstalk
f
CLK
= 100MSPS, f
OUT
= 10MHz
f
CLK
= 100MSPS, f
OUT
= 40MHz
f
CLK
= 260MSPS, f
OUT
= 40.4MHz
Gain Matching Between Channels
(DC Measurement)
Full Scale Output Current, I
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
As a percentage of Full Scale Range
In dB Full Scale Range
260
Full Scale Step
Full Scale Step
-
-
-
IOUTFS = 20mA
IOUTFS = 2mA
-
-
300
1
1
5
50
30
-
-
-
-
-
-
MHz
ns
ns
pF
pA/√Hz
pA/√Hz
5
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