®
ISL6142, ISL6152
Data Sheet
July 2004
FN9086.1
Negative Voltage Hot Plug Controller
The ISL6142/52 are 14 pin, negative voltage hot plug controllers
that allow a board to be safely inserted and removed from a live
backplane. Inrush current is limited to a programmable value by
controlling the gate voltage of an external N-channel pass
transistor. The pass transistor is turned off if the input voltage is
less than the Under-Voltage threshold, or greater than the Over-
Voltage threshold. The PWRGD/PWRGD outputs can be used to
directly enable a power module. When the Gate and DRAIN
voltages are both considered good the output is latched in the
active state.
The IntelliTrip
TM
electronic circuit breaker and programmable
current limit features protect the system against short circuits.
When the Over-Current threshold is exceeded, the output current
is limited for a time-out period before the circuit breaker trips and
shuts down the FET. The time-out period is programmable with an
external capacitor connected to the CT pin. If the fault disappears
before the programmed time-out, normal operation resumes. In
addition, the IntelliTrip
TM
electronic circuit breaker has a fast Hard
Fault shutdown, with a threshold set at 4 times the Over-Current
trip point. When activated, the GATE is immediately turned off and
then slowly turned back on for a single retry.
The IS+, IS-, and IS
OUT
pins combine to provide a load current
monitor feature that presents a scaled version of the load current
at the IS
OUT
pin. Current to voltage conversion is accomplished
by placing a resistor (R9) from IS
OUT
to the negative input (-48V).
Typical Application
Logic
Supply
GND
FAULT
DIS
R10
R4
UV
R5
OV
R6
CT V
EE
IS-
IS+ SENSE GATE
DRAIN
LOAD
R9
C3
R7
R8
C1
R3 C2
R2
CL
RL
-48V IN
R1
Q1
-48V OUT
IS
OUT
V
DD
GND
PWRGD
PWRGD
ISL6142/ISL6152
R1 = 0.02Ω (1%)
R2 = 10Ω (5%)
R3 = 18KΩ (5%)
R4 = 549KΩ (1%)
R5 = 6.49KΩ (1%)
R6 = 10KΩ (1%)
R7 = R8 = 400Ω (1%)
R9 = 4.99KΩ (1%)
R10 = 5.1KΩ (10%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
C3 = 1500pF (25V)
Q1 = IRF530
CL = 100uF (100V)
RL = Equivalent load
Features
• Operates from -20V to -80V (-100V Absolute Max Rating)
• Programmable Inrush Current
• Programmable Time-Out
• Programmable Current Limit
• Programmable Over-Voltage Protection
• Programmable Under-Voltage Protection
- 135 mV of hysteresis ~4.7V of hysteresis at the power supply
• V
DD
Under-Voltage Lock-Out (UVLO) ~ 16.5V
• IntelliTrip
TM
Electronic Circuit Breaker distinguishes between
severe and moderate faults
- Fast shutdown for short circuit faults with a single retry (fault
current > 4X current limit value).
• FAULT pin reports the occurrence of an Over-Current Time-Out
• Disable input controls GATE shutdown and resets Over-Current
fault latch
• Load Current Monitor Function
- IS
OUT
provides a scaled version of the load current
- A resistor from IS
OUT
to -V
IN
provides current to voltage
conversion
• Power Good Control Output
- Output latched “good” when DRAIN and GATE voltage
thresholds are met.
- (PWRGD active low: ISL6142 (L version)
- PWRGD active high: ISL6152 (H version)
• Pb-free available
Related Literature
•
•
•
•
•
•
ISL6142/52EVAL1 Board Set, Document AN1000
ISL6140/50EVAL1 Board Set, Document AN9967
ISL6140/41EVAL1 Board Set, Document AN1020
ISL6141/51 Hot Plug Controller, Document FN9079
ISL6141/51 Hot Plug Controller, Document FN9039
ISL6116 Hot Plug Controller, Document FN4778
NOTE: See www.intersil.com/hotplug for more information.
Pinout
ISL6142 OR ISL6152 (14 LEAD SOIC)
PWRGD/PWRGD 1
FAULT 2
DIS
OV
UV
IS-
V
EE
3
4
5
6
7
ISL6142/52
Top View
14 V
DD
13 CT
12 IS
OUT
11 DRAIN
10 GATE
9
8
IS+
SENSE
Applications
•
•
•
•
1
VoIP (Voice over Internet Protocol) Servers
Telecom systems at -48V
Negative Power Supply Control
+24V Wireless Base Station Power
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a registered trademark of Intersil Americas Inc.
Intellitrip™ is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004, All Rights Reserved
ISL6142, ISL6152
Ordering Information
PART NUMBER
ISL6142CB
ISL6142CBZA
(See Note)
ISL6152CB
ISL6152CBZA
(See Note)
ISL6142IB
ISL6142IBZA
(See Note)
ISL6152IB
ISL6152IBZA
(See Note)
TEMP. RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PACKAGE
PKG.
DWG. #
14 Lead SOIC M14.15
14 Lead SOIC M14.15
(Pb-free)
14 Lead SOIC M14.15
14 Lead SOIC M14.15
(Pb-free)
14 Lead SOIC M14.15
14 Lead SOIC M14.15
(Pb-free)
14 Lead SOIC M14.15
14 Lead SOIC M14.15
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
2
ISL6142, ISL6152
ISL6142, ISL6152 Block Diagram
GND
GND
V
DD
-
R4
V
EE
1.265V
+
+
-
UVLO
REGULATOR,
REFERENCES
UV
V
EE
-
1.255V
+
UV
13V
R5
OV
+
-
V
EE
+
1.255V
+
-
V
EE
OV
LOGIC,
TIMING,
GATE
DRIVE
HARD
FAULT
-
-
R6
210mV
+
-
V
EE
+
GATE
11.1V
+
-
V
EE
-
+
(ISL6142)
-
PWRGD
-
LOGIC
SUPPLY
R10
50mV
+
+
-
V
EE
CURRENT
LIMIT
REGULATOR
1.3V
+
-
V
EE
+
LATCH,
LOGIC,
OUTPUT
DRIVE
PWRGD
(ISL6152)
FAULT
FAULT
-
DIS
LOGIC
INPUT
V
EE
8.0V
+
DISABLE
V
EE+5V
13V
-
+
-
V
EE
CT
8.5V
+
-
V
EE
TIMER
+
C3
V
EE
STOP GATE
TO ADC
IS
OUT
V
EE
R7
CURRENT
SENSE
IS-
R8
IS+
SENSE
C1
R2
GATE
R3
C2
DRAIN
LOAD
CL
RL
R9
-48V IN
R1
Q1
-48V OUT
FIGURE 1. BLOCK DIAGRAM
3
ISL6142, ISL6152
Pin Descriptions
PWRGD (ISL6142; L Version) Pin 1 -
This digital output is
an open-drain pull-down device and can be used to directly
enable an external module. During start-up the DRAIN and
GATE voltages are monitored with two separate comparators.
The first comparator looks at the DRAIN pin voltage compared
to the internal V
PG
reference (1.3V); this measures the
voltage drop across the external FET and sense resistor.
When the DRAIN to V
EE
voltage drop is less than 1.3V, the
first of two conditions required for the power to be considered
good are met. In addition, the GATE voltage monitored by the
second comparator must be within approximately 2.5V of its
normal operating voltage (13.6V). When both criteria are met
the PWRGD output will transition low and be latched in the
active state, enabling the external module. When this occurs
the two comparators discussed above no longer control the
output. However a third comparator continues to monitor the
DRAIN voltage, and will drive the PWRGD output inactive if
the DRAIN voltage raises more than 8V above V
EE
. In
addition, any of the signals that shut off the GATE (Over-
Voltage, Under-Voltage, Under-Voltage Lock-Out, Over-
Current time-out, pulling the DIS pin high, or powering down)
will reset the latch and drive the PWRGD output high to
disable the module. In this case, the output pull-down device
shuts off, and the pin becomes high impedance. Typically an
external pull-up of some kind is used to pull the pin high (many
brick regulators have a pull-up function built in).
PWRGD (ISL6152; H Version) Pin 1 -
This digital output is
used to provide an active high signal to enable an external
module. The Power Good comparators are the same as
described above, but the active state of the output is
reversed (reference figure 37).
When power is considered good (both DRAIN and GATE are
normal) the output is latched in the active high state, the
DMOS device (Q3) turns on and sinks current to V
EE
through
a 6.2KΩ resistor. The base of Q2 is clamped to V
EE
to turn it
off. If the external pull-up current is high enough (>1mA, for
example), the voltage drop across the resistor will be large
enough to produce a logic high output and enable the external
module (in this example, 1mA x 6.2KΩ = 6.2V).
Note that for all H versions, although this is a digital pin
functionally, the logic high level is determined by the external
pull-up device, and the power supply to which it is
connected; the IC will not clamp it below the V
DD
voltage.
Therefore, if the external device does not have its own
clamp, or if it would be damaged by a high voltage, an
external clamp might be necessary.
If the power good latch is reset (GATE turns off), the internal
DMOS device (Q3) is turned off, and Q2 (NPN) turns on to
clamp the output one diode drop above the DRAIN voltage to
produce a logic low, indicating power is no longer good.
FAULT Pin 2-
This digital output is an open-drain, pull-down
device, referenced to V
EE
. It is pulled active low whenever
the Over-Current latch is set. It goes to a high impedance
state when the fault latch is reset by toggling the UV or DIS
pins. An external pull-up resistor to a logic supply (5V or
less) is required; the fault outputs of multiple IC’s can be
wire-OR’d together. If the pin is not used it should be left
open.
DIS Pin 3 -
This digital input disables the FET when driven to
a logic high state. It has a weak internal pull-up device to an
internal 5V rail (10µA), so an open pin will also act as a logic
high. The input has a nominal trip point of 1.6 V while rising,
and a hysteresis of 1.0V. The threshold voltage is referenced
to V
EE
, and is compatible with CMOS logic levels. A logic
low will allow the GATE to turn on (assuming the 4 other
conditions described in the GATE section are also true). The
DIS pin can also be used to reset the Over-Current latch
when toggled high to low. If not used the pin should be tied to
the negative supply rail (-V
IN
).
OV (Over-Voltage) Pin 4 -
This analog input compares the
voltage on the pin to an internal voltage reference of 1.255 V
(nominal). When the input goes above the reference the
GATE pin is immediately pulled low to shut off the external
FET. The built in 25mV hysteresis will keep the GATE off until
the OV pin drops below 1.230V (the nominal high to low
threshold). A typical application will use an external resistor
divider from V
DD
to -V
IN
to set the OV trip level. A three-
resistor divider can be used to set both OV and UV trip
points to reduce component count.
UV (Under-Voltage) Pin 5 -
This analog input compares the
voltage on the pin to an internal comparator with a built in
hysteresis of 135mv. When the UV input goes below the
nominal reference voltage of 1.120V, the GATE pin is
immediately pulled low to shut off the external FET. The
GATE will remain off until the UV pin rises above a 1.255V
low to high threshold. A typical application will use an
external resistor divider from V
DD
to -V
IN
to set the UV level
as desired. A three-resistor divider can be used to set both
OV and UV trip points to reduce component count.
The UV pin is also used to reset the Over-Current latch. The
pin must be cycled below 1.120V (nominal) and then above
1.255V (nominal) to clear the latch and initiate a normal
start-up sequence.
IS- Pin 6 -
This analog pin is the negative input of the current
sense circuit. A sensing resistor (R7) is connected between
this pin and the V
EE
side of resistor R1. The ratio of R1/R7
defines the I
SENSE
to IS
OUT
current scaling factor. If current
sensing is not used in the application, the IS- pin should be
tied directly to the IS+ pin and the node should be left
floating.
4
ISL6142, ISL6152
V
EE
Pin 7 -
This is the most Negative Supply Voltage, such
as in a -48V system. Most of the other signals are referenced
relative to this pin, even though it may be far away from what
is considered a GND reference.
SENSE Pin 8 -
This analog input monitors the voltage drop
across the external sense resistor to determine if the current
flowing through it exceeds the programmed Over-Current trip
point (50mV / Rsense). If the Over-Current threshold is
exceeded, the circuit will regulate the current to maintain a
nominal voltage drop of 50mV across the R1 sense resistor,
also referred to as Rsense. If current is limited for more than
the programmed time-out period the
IntelliTrip
TM
electronic
circuit breaker
will trip and turn off the FET.
A second comparator is employed to detect and respond
quickly to hard faults. The threshold of this comparator is set
approximately four times higher (210mV) than the Over-
Current trip point. When the hard fault comparator threshold
is exceeded the GATE is immediately (10µs typical) shut off
(V
GATE
= V
EE
), the timer is reset, and a single retry (soft
start) is initiated.
IS+ Pin 9 -
This analog pin is the positive input of the current
sense circuit. A sensing resistor (R8) is connected between
this pin and the output side of R1, which is also connected to
the SENSE pin. It should match the IS- resistor (R7) as
closely as possible (1%) to minimize output current error
(IS
OUT
). If current sensing is not used in the application, the
IS+ pin should be tied directly to the IS- pin and the node
should be left floating.
GATE Pin 10 -
This
analog output drives the gate of the
external FET used as a pass transistor. The GATE pin is high
(FET is on) when the following conditions are met:
•
•
•
•
•
V
DD
UVLO is above its trip point (~16.5V)
Voltage on the UV pin is above its trip point (1.255V)
Voltage on the OV pin is below its trip point (1.255V)
No Over-Current conditions are present.
The Disable pin is low.
1.3v and 8.0V. At initial start-up the DRAIN to V
EE
voltage
differential must be less than 1.3V, and the GATE voltage
must be within 2.5V of its normal operating voltage (13.6V)
for power to be considered good. When both conditions are
met, the PWRGD/PWRGD output is latched into the active
state. At this point only the 8V DRAIN comparator can
control the PWRGD/PWRGD output, and will drive it inactive
if the DRAIN voltage exceeds V
EE
by more than 8.0V.
IS
OUT
Pin 12 -
This analog pin is the output of the current
sense circuit. The current flowing out of this pin (IS
OUT
) is
proportional to the current flowing through the R1 sense
resistor (I
SENSE
). The scaling factor, IS
OUT
/I
SENSE
is
defined by the resistor ratio of R1/R7. Current to voltage
conversion is accomplished by placing a resistor from this
pin to -V
IN
. The current flowing out of the pin is supplied by
the internal 13V regulator and should not exceed 600µA.
The output voltage will clamp at approximately 8V. If current
sensing is not used in the application the pin should be left
open.
CT Pin 13 -
This analog I/O pin is used to program the Over-
Current Time-Out period with a capacitor connected to the
negative supply rail (-V
IN
which is equal to V
EE
). During
normal operation, the pin is pulled down to V
EE
. During
current limiting, the capacitor is charged with a 20µA
(nominal) current source. When the CT pin charges to 8.5V,
it times out and the GATE is latched off. If the short circuit
goes away prior to the time-out, the GATE will remain on. If
no capacitor is connected, the time-out will be much quicker,
with only the package pin capacitance (~ 5 to 10 pF) to
charge. If no external capacitor is connected to the CT pin
the time-out will occur in a few
µsec.
To set the desired time-
out period use:
dt = (C * dV) / I = (C * 8.5) / 20
µA
= 0.425*10
6
* C
NOTE: The printed circuit board’s parasitic capacitance (CT pin to
the negative input, -V
IN
) should be taken into consideration when
calculating the value of C3 needed for the desired time-out.
If any of the 5 conditions are violated, the GATE pin will be
pulled low to shut off or regulate current through the FET.
The GATE is latched off only when an Over-Current event
exceeds the programmed time-out period.
The GATE is driven high by a weak (-50µA nominal) pull-up
current source, in order to slowly turn on the FET. It is driven
low by a 70mA (nominal) pull-down device for three of the
above shut-off conditions. A larger (350mA nominal) pull-
down current shuts off the FET very quickly in the event of a
hard fault where the sense pin voltage exceeds
approximately 210mV.
DRAIN Pin 11 -
This analog input monitors the voltage of
the FET drain for the Power Good function. The DRAIN input
is tied to two comparators with internal reference voltages of
V
DD
Pin 14 -
This is the most positive Power Supply pin. It
can range from the Under-Voltage lockout threshold (16.5V)
to +80V (Relative to V
EE
). The pin can tolerate up to 100V
without damage to the IC.
5
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