®
ISL6413
Data Sheet
October 2003
FN9129
PRELIMINARY
Triple Output Regulator with Single
Synchronous Buck and Dual LDO
The ISL6413 is a highly integrated triple output regulator
which provides a single chip solution for wireless chipset
power management. The device integrates high efficiency
synchronous buck regulator with two ultra low noise LDO
regulators. The IC accepts an input voltage range of 3.0V to
3.6V and provides three regulated output voltages: 1.8V
(PWM), 2.84V (LDO1), and another ultra-clean 2.84V
(LDO2).
The Synchronous current mode PWM regulator with
integrated N- and P-channel power MOSFET provides pre-
set 1.8V for BBP/MAC core supply. Synchronous
rectification with internal MOSFETs is used to achieve higher
efficiency and reduced number of external components.
Operating frequency is typically 750kHz allowing the use of
smaller inductor and capacitor values. The device can be
synchronized to an external clock signal in the range of
500kHz to 1MHz. The PG_PWM output indicates loss of
regulation on PWM output.
The ISL6413 also has two LDO regulators which use an
internal PMOS transistor as the pass device. LDO2 features
ultra low noise that does not typically exceed 30µV RMS to
aid VCO stability. The EN_LDO pin controls LDO1 and
LDO2 outputs. The ISL6413 also integrates a RESET
function, which eliminates the need for additional RESET IC
required in WLAN applications. The IC asserts a RESET
signal whenever the V
IN
supply voltage drops below a preset
threshold, keeping it asserted for at least 25ms after V
IN
has
risen above the reset threshold. The PG_LDO output
indicates loss of regulation on either of the two LDO outputs.
Other features include over current protection for all three
outputs and thermal shutdown.
High integration and the thin Quad Flat No-lead (QFN)
package makes ISL6413 an ideal choice to power many of
today’s small form factor industry standard wireless cards
such as PCMCIA, mini-PCI and Cardbus-32.
Features
• Fully Integrated Synchronous Buck Regulator + Dual LDO
• High Output Current (For QFN package)
- PWM, 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA
- LDO1, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
- LDO2, 2.84V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
• Ultra-Compact DC-DC Converter Design
• Stable with Small Ceramic Output Capacitors
• High conversion efficiency
• Low Shutdown supply current
• Ultra-Low Dropout Voltage for LDOs
- LDO1, 2.84V. . . . . . . . . . . . . . . 125mV (typ.) at 300mA
- LDO2, 2.84V. . . . . . . . . . . . . . . 100mV (typ.) at 200mA
• Ultra-Low Output Voltage Noise
- <30µV
RMS
(typ.) for LDO2 (VCO Supply)
• PG_LDO, PG_PWM and PG_PWM outputs
• Extensive circuit protection and monitoring features
- Over voltage protection
- Over current protection
- Shutdown
- Thermal Shutdown
• Integrated RESET output for microprocessor reset
• Proven Reference Design for Total WLAN System
Solution
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint Improves PCB
Efficiency and Is Thinner in Profile
Applications
• WLAN Cards
- PCMCIA, Cardbus32, MiniPCI Cards
- Compact Flash Cards
• Liberty Chipset
• Hand-Held Instruments
Ordering Information
PART NUMBER TEMP. RANGE (
o
C) PACKAGE PKG. DWG. #
ISL6413IR
-40 to 85
24 Ld QFN L24.4x4B
Related Literature
• TB363 - Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)
• TB389 - PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6413
Absolute Maximum Ratings
(Note 1)
Supply Voltage VIN, PV
CC
, VIN _LDO. . . . . . . . GND -0.3V to +5.0V
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBDV
Thermal Information
Thermal Resistance
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
QFN Package (Notes 1, 2). . . . . . . . . .
40
5
Maximum Junction Temperature (Plastic Package) -55
o
C to 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(Lead Tips Only)
Operating Temperature Range
ISL6413IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Operating Conditions
Temperature Range
ISL6413I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379 for details.
2.
For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
V
CC
SUPPLY
Supply Voltage Range
Input UVLO Threshold
Recommended operating conditions unless otherwise noted. V
IN
= V
IN
_LDO = PV
CC
= 3.3V, Compensation
Capacitors = 33nF for LDO1 and LDO2. T
A
= 25
o
C. (Note 2)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN, PV
CC
, VIN _LDO
V
TR
V
TF
3.0
2.55
2.5
-
-
-
-
-
-
-
-
3.3
2.62
2.55
0.9
1.9
15
20
1.0
1.5
150
20
3.6
2.66
2.59
1.1
2.5
20
25
1.5
2.0
-
25
V
V
V
mA
mA
µA
µA
µA
µA
o
C
o
C
Operating Supply Current (Note 3)
Device active, but not switching
V
IN
= V
IN
_LDO = PV
CC
= 3.3V
f
SW
= 750kHz, C
OUT
= 10µF, I
L
= 0mA
Shutdown Supply Current
EN_PWM = EN_LDO = GND, T
A
= 25
o
C
EN_PWM = EN_LDO = GND, T
A
= 85
o
C
EN_PWM = EN_LDO = GND/V
IN
, T
A
= 25
o
C
EN_PWM = EN_LDO = GND/V
IN
, T
A
= 85
o
C
Input Bias Current
Thermal Shutdown Temperature (Note 6)
Thermal Shutdown Hysteresis (Note 6)
SYNCHRONOUS BUCK PWM REGULATOR
Output Voltage
Output Voltage Accuracy
Line Regulation
Maximum Output Current
Peak Output Current Limit
PMOS r
DS(ON)
NMOS r
DS(ON)
Efficiency
Soft-Start Time
OSCILLATOR
Oscillator Frequency
Frequency Synchronization Range (f
SYNC
)
SYNC High Level Input Voltage
SYNC Low Level Input Voltage
Rising Threshold
-
I
OUT
= 3mA to 400mA, T
A
= -40
o
C to 85
o
C
I
O
= 10mA, V
IN
= V
IN
_LDO = PV
CC
= 3.0V to 3.6V
-2.0
-0.5
400
600
I
OUT
= 200mA
I
OUT
= 200mA
I
OUT
= 200mA, V
IN
= 3.3V
4096 Clock Cycles @ 750kHz
-
-
-
-
1.8
-
-
-
-
300
225
93
5.5
-
2.0
0.5
-
900
-
-
-
-
V
%
%
mA
mA
mΩ
mΩ
%
ms
T
A
= -40
o
C to +85
o
C
Clock signal on SYNC pin
620
500
2.3
-
750
-
-
-
860
1000
-
1.0
kHz
kHz
V
V
4
ISL6413
Electrical Specifications
PARAMETER
Sync Input Leakage Current
Duty Cycle of External Clock Signal (Note 6)
PG_PWM
Rising Threshold
Falling Threshold
LDO1 SPECIFICATIONS
Output Voltage
Output Voltage Accuracy
Maximum Output Current (Note 6)
Output Current Limit (Note 6)
Dropout Voltage (Note 4)
Line Regulation
Load Regulation
Output Voltage Noise (Note 6)
I
OUT
= 300mA
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
I
OUT
= 10mA to 300mA
10Hz < f < 100kHz, I
OUT
= 10mA
C
OUT
= 2.2µF
C
OUT
= 10µF
LDO2 SPECIFICATIONS
Output Voltage
Output Voltage Accuracy
Maximum Output Current (Note 6)
Output Current Limit (Note 6)
Dropout Voltage (Note 4)
Line Regulation
Load Regulation
Output Voltage Noise (Note 6)
I
OUT
= 200mA
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
I
OUT
= 10mA to 200mA
10Hz < f < 100kHz, I
OUT
= 10mA
C
OUT
= 2.2µF
C
OUT
= 10µF
ENABLE (EN_PWM and (EN_LDO)
EN High Level Input Voltage
EN Low Level Input Voltage
RESET BLOCK SPECIFICATIONS
RESET Rising Threshold
RESET Falling Threshold
RESET Threshold Hysteresis
RESET Current Source
RESET/RESET Active Timeout Period (Note 5)
POWER GOOD (PG_LDO)
PGOOD Threshold (Rising)
PGOOD Threshold (Falling)
PGOOD Output Voltage Low
I
OL
= 1mA
+11
-17
-
+15
-15
-
+18
-11
0.5
%
%
V
C
T
= 0.01µF
Sink 1.0mA/Source 0.5mA at 0.4V from GND/V
DD
2.68
2.7
-
0.4
25
2.79
2.77
20
0.54
-
2.81
2.79
-
0.7
-
V
V
mV
µA
ms
2.3
-
-
-
-
1.0
V
V
-
-
30
20
-
-
µV
RMS
µV
RMS
I
OUT
= 10mA
VIN = 3.6V
-
-1.5
200
250
-
-0.15
-
2.84
-
-
400
100
0.0
0.2
-
1.5
-
-
200
0.15
1.0
V
%
mA
mA
mV
%/V
%
-
-
65
60
-
-
µV
RMS
µV
RMS
I
OUT
= 10mA
VIN = 3.6V
-
-1.5
300
330
-
-0.15
-0.5
2.84
-
-
770
125
0.0
0.2
-
1.5
-
-
200
0.15
1.0
V
%
mA
mA
mV
%/V
%
1mA source/sink
+5.5
-11.5
8.0
-8.0
+13
-5.5
%
%
Recommended operating conditions unless otherwise noted. V
IN
= V
IN
_LDO = PV
CC
= 3.3V, Compensation
Capacitors = 33nF for LDO1 and LDO2. T
A
= 25
o
C. (Note 2)
(Continued)
TEST CONDITIONS
SYNC = GND or V
IN
MIN
-
20
TYP
0.01
-
MAX
0.15
80
UNITS
µA
%
5
Power technology
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